TouchDisplay.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001e4 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 0000414c 080001e4 080001e4 000011e4 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000040 08004330 08004330 00005330 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08004370 08004370 0000600c 2**0 CONTENTS 4 .ARM 00000000 08004370 08004370 0000600c 2**0 CONTENTS 5 .preinit_array 00000000 08004370 08004370 0000600c 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08004370 08004370 00005370 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 7 .fini_array 00000004 08004374 08004374 00005374 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 8 .data 0000000c 20000000 08004378 00006000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00000198 2000000c 08004384 0000600c 2**2 ALLOC 10 ._user_heap_stack 00000604 200001a4 08004384 000061a4 2**0 ALLOC 11 .ARM.attributes 00000029 00000000 00000000 0000600c 2**0 CONTENTS, READONLY 12 .debug_info 0000c56f 00000000 00000000 00006035 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 000024cf 00000000 00000000 000125a4 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00000b70 00000000 00000000 00014a78 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_rnglists 000008a4 00000000 00000000 000155e8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 00019e42 00000000 00000000 00015e8c 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 0000dfcd 00000000 00000000 0002fcce 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 00095fa6 00000000 00000000 0003dc9b 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000043 00000000 00000000 000d3c41 2**0 CONTENTS, READONLY 20 .debug_frame 00002ce4 00000000 00000000 000d3c84 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 21 .debug_line_str 0000005c 00000000 00000000 000d6968 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080001e4 <__do_global_dtors_aux>: 80001e4: b510 push {r4, lr} 80001e6: 4c05 ldr r4, [pc, #20] @ (80001fc <__do_global_dtors_aux+0x18>) 80001e8: 7823 ldrb r3, [r4, #0] 80001ea: b933 cbnz r3, 80001fa <__do_global_dtors_aux+0x16> 80001ec: 4b04 ldr r3, [pc, #16] @ (8000200 <__do_global_dtors_aux+0x1c>) 80001ee: b113 cbz r3, 80001f6 <__do_global_dtors_aux+0x12> 80001f0: 4804 ldr r0, [pc, #16] @ (8000204 <__do_global_dtors_aux+0x20>) 80001f2: f3af 8000 nop.w 80001f6: 2301 movs r3, #1 80001f8: 7023 strb r3, [r4, #0] 80001fa: bd10 pop {r4, pc} 80001fc: 2000000c .word 0x2000000c 8000200: 00000000 .word 0x00000000 8000204: 08004318 .word 0x08004318 08000208 : 8000208: b508 push {r3, lr} 800020a: 4b03 ldr r3, [pc, #12] @ (8000218 ) 800020c: b11b cbz r3, 8000216 800020e: 4903 ldr r1, [pc, #12] @ (800021c ) 8000210: 4803 ldr r0, [pc, #12] @ (8000220 ) 8000212: f3af 8000 nop.w 8000216: bd08 pop {r3, pc} 8000218: 00000000 .word 0x00000000 800021c: 20000010 .word 0x20000010 8000220: 08004318 .word 0x08004318 08000224
: /** * @brief The application entry point. * @retval int */ int main(void) { 8000224: b580 push {r7, lr} 8000226: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8000228: f000 fb90 bl 800094c /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 800022c: f000 f81a bl 8000264 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000230: f000 f910 bl 8000454 MX_USART1_UART_Init(); 8000234: f000 f890 bl 8000358 MX_USART2_UART_Init(); 8000238: f000 f8b8 bl 80003ac MX_USART3_UART_Init(); 800023c: f000 f8e0 bl 8000400 MX_CRC_Init(); 8000240: f000 f856 bl 80002f0 MX_SDIO_SD_Init(); 8000244: f000 f868 bl 8000318 MX_FATFS_Init(); 8000248: f003 fe46 bl 8003ed8 /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { HAL_GPIO_TogglePin(GPIOC, GPIO_PIN_4); 800024c: 2110 movs r1, #16 800024e: 4804 ldr r0, [pc, #16] @ (8000260 ) 8000250: f001 f831 bl 80012b6 HAL_Delay(500); 8000254: f44f 70fa mov.w r0, #500 @ 0x1f4 8000258: f000 fbda bl 8000a10 HAL_GPIO_TogglePin(GPIOC, GPIO_PIN_4); 800025c: bf00 nop 800025e: e7f5 b.n 800024c 8000260: 40011000 .word 0x40011000 08000264 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000264: b580 push {r7, lr} 8000266: b090 sub sp, #64 @ 0x40 8000268: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 800026a: f107 0318 add.w r3, r7, #24 800026e: 2228 movs r2, #40 @ 0x28 8000270: 2100 movs r1, #0 8000272: 4618 mov r0, r3 8000274: f004 f824 bl 80042c0 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000278: 1d3b adds r3, r7, #4 800027a: 2200 movs r2, #0 800027c: 601a str r2, [r3, #0] 800027e: 605a str r2, [r3, #4] 8000280: 609a str r2, [r3, #8] 8000282: 60da str r2, [r3, #12] 8000284: 611a str r2, [r3, #16] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 8000286: 2301 movs r3, #1 8000288: 61bb str r3, [r7, #24] RCC_OscInitStruct.HSEState = RCC_HSE_ON; 800028a: f44f 3380 mov.w r3, #65536 @ 0x10000 800028e: 61fb str r3, [r7, #28] RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV2; 8000290: f44f 3300 mov.w r3, #131072 @ 0x20000 8000294: 623b str r3, [r7, #32] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 8000296: 2301 movs r3, #1 8000298: 62bb str r3, [r7, #40] @ 0x28 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 800029a: 2302 movs r3, #2 800029c: 637b str r3, [r7, #52] @ 0x34 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 800029e: f44f 3380 mov.w r3, #65536 @ 0x10000 80002a2: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; 80002a4: f44f 13e0 mov.w r3, #1835008 @ 0x1c0000 80002a8: 63fb str r3, [r7, #60] @ 0x3c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 80002aa: f107 0318 add.w r3, r7, #24 80002ae: 4618 mov r0, r3 80002b0: f001 f81a bl 80012e8 80002b4: 4603 mov r3, r0 80002b6: 2b00 cmp r3, #0 80002b8: d001 beq.n 80002be { Error_Handler(); 80002ba: f000 f949 bl 8000550 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 80002be: 230f movs r3, #15 80002c0: 607b str r3, [r7, #4] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 80002c2: 2302 movs r3, #2 80002c4: 60bb str r3, [r7, #8] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 80002c6: 2300 movs r3, #0 80002c8: 60fb str r3, [r7, #12] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 80002ca: f44f 6380 mov.w r3, #1024 @ 0x400 80002ce: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 80002d0: 2300 movs r3, #0 80002d2: 617b str r3, [r7, #20] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 80002d4: 1d3b adds r3, r7, #4 80002d6: 2102 movs r1, #2 80002d8: 4618 mov r0, r3 80002da: f001 fa87 bl 80017ec 80002de: 4603 mov r3, r0 80002e0: 2b00 cmp r3, #0 80002e2: d001 beq.n 80002e8 { Error_Handler(); 80002e4: f000 f934 bl 8000550 } } 80002e8: bf00 nop 80002ea: 3740 adds r7, #64 @ 0x40 80002ec: 46bd mov sp, r7 80002ee: bd80 pop {r7, pc} 080002f0 : * @brief CRC Initialization Function * @param None * @retval None */ static void MX_CRC_Init(void) { 80002f0: b580 push {r7, lr} 80002f2: af00 add r7, sp, #0 /* USER CODE END CRC_Init 0 */ /* USER CODE BEGIN CRC_Init 1 */ /* USER CODE END CRC_Init 1 */ hcrc.Instance = CRC; 80002f4: 4b06 ldr r3, [pc, #24] @ (8000310 ) 80002f6: 4a07 ldr r2, [pc, #28] @ (8000314 ) 80002f8: 601a str r2, [r3, #0] if (HAL_CRC_Init(&hcrc) != HAL_OK) 80002fa: 4805 ldr r0, [pc, #20] @ (8000310 ) 80002fc: f000 fcb9 bl 8000c72 8000300: 4603 mov r3, r0 8000302: 2b00 cmp r3, #0 8000304: d001 beq.n 800030a { Error_Handler(); 8000306: f000 f923 bl 8000550 } /* USER CODE BEGIN CRC_Init 2 */ /* USER CODE END CRC_Init 2 */ } 800030a: bf00 nop 800030c: bd80 pop {r7, pc} 800030e: bf00 nop 8000310: 20000028 .word 0x20000028 8000314: 40023000 .word 0x40023000 08000318 : * @brief SDIO Initialization Function * @param None * @retval None */ static void MX_SDIO_SD_Init(void) { 8000318: b480 push {r7} 800031a: af00 add r7, sp, #0 /* USER CODE END SDIO_Init 0 */ /* USER CODE BEGIN SDIO_Init 1 */ /* USER CODE END SDIO_Init 1 */ hsd.Instance = SDIO; 800031c: 4b0c ldr r3, [pc, #48] @ (8000350 ) 800031e: 4a0d ldr r2, [pc, #52] @ (8000354 ) 8000320: 601a str r2, [r3, #0] hsd.Init.ClockEdge = SDIO_CLOCK_EDGE_RISING; 8000322: 4b0b ldr r3, [pc, #44] @ (8000350 ) 8000324: 2200 movs r2, #0 8000326: 605a str r2, [r3, #4] hsd.Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE; 8000328: 4b09 ldr r3, [pc, #36] @ (8000350 ) 800032a: 2200 movs r2, #0 800032c: 609a str r2, [r3, #8] hsd.Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; 800032e: 4b08 ldr r3, [pc, #32] @ (8000350 ) 8000330: 2200 movs r2, #0 8000332: 60da str r2, [r3, #12] hsd.Init.BusWide = SDIO_BUS_WIDE_1B; 8000334: 4b06 ldr r3, [pc, #24] @ (8000350 ) 8000336: 2200 movs r2, #0 8000338: 611a str r2, [r3, #16] hsd.Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; 800033a: 4b05 ldr r3, [pc, #20] @ (8000350 ) 800033c: 2200 movs r2, #0 800033e: 615a str r2, [r3, #20] hsd.Init.ClockDiv = 0; 8000340: 4b03 ldr r3, [pc, #12] @ (8000350 ) 8000342: 2200 movs r2, #0 8000344: 619a str r2, [r3, #24] /* USER CODE BEGIN SDIO_Init 2 */ /* USER CODE END SDIO_Init 2 */ } 8000346: bf00 nop 8000348: 46bd mov sp, r7 800034a: bc80 pop {r7} 800034c: 4770 bx lr 800034e: bf00 nop 8000350: 20000030 .word 0x20000030 8000354: 40018000 .word 0x40018000 08000358 : * @brief USART1 Initialization Function * @param None * @retval None */ static void MX_USART1_UART_Init(void) { 8000358: b580 push {r7, lr} 800035a: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 800035c: 4b11 ldr r3, [pc, #68] @ (80003a4 ) 800035e: 4a12 ldr r2, [pc, #72] @ (80003a8 ) 8000360: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 8000362: 4b10 ldr r3, [pc, #64] @ (80003a4 ) 8000364: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8000368: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 800036a: 4b0e ldr r3, [pc, #56] @ (80003a4 ) 800036c: 2200 movs r2, #0 800036e: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 8000370: 4b0c ldr r3, [pc, #48] @ (80003a4 ) 8000372: 2200 movs r2, #0 8000374: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 8000376: 4b0b ldr r3, [pc, #44] @ (80003a4 ) 8000378: 2200 movs r2, #0 800037a: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 800037c: 4b09 ldr r3, [pc, #36] @ (80003a4 ) 800037e: 220c movs r2, #12 8000380: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8000382: 4b08 ldr r3, [pc, #32] @ (80003a4 ) 8000384: 2200 movs r2, #0 8000386: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 8000388: 4b06 ldr r3, [pc, #24] @ (80003a4 ) 800038a: 2200 movs r2, #0 800038c: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 800038e: 4805 ldr r0, [pc, #20] @ (80003a4 ) 8000390: f002 fb4c bl 8002a2c 8000394: 4603 mov r3, r0 8000396: 2b00 cmp r3, #0 8000398: d001 beq.n 800039e { Error_Handler(); 800039a: f000 f8d9 bl 8000550 } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 800039e: bf00 nop 80003a0: bd80 pop {r7, pc} 80003a2: bf00 nop 80003a4: 200000b4 .word 0x200000b4 80003a8: 40013800 .word 0x40013800 080003ac : * @brief USART2 Initialization Function * @param None * @retval None */ static void MX_USART2_UART_Init(void) { 80003ac: b580 push {r7, lr} 80003ae: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 80003b0: 4b11 ldr r3, [pc, #68] @ (80003f8 ) 80003b2: 4a12 ldr r2, [pc, #72] @ (80003fc ) 80003b4: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; 80003b6: 4b10 ldr r3, [pc, #64] @ (80003f8 ) 80003b8: f44f 32e1 mov.w r2, #115200 @ 0x1c200 80003bc: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 80003be: 4b0e ldr r3, [pc, #56] @ (80003f8 ) 80003c0: 2200 movs r2, #0 80003c2: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 80003c4: 4b0c ldr r3, [pc, #48] @ (80003f8 ) 80003c6: 2200 movs r2, #0 80003c8: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 80003ca: 4b0b ldr r3, [pc, #44] @ (80003f8 ) 80003cc: 2200 movs r2, #0 80003ce: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 80003d0: 4b09 ldr r3, [pc, #36] @ (80003f8 ) 80003d2: 220c movs r2, #12 80003d4: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80003d6: 4b08 ldr r3, [pc, #32] @ (80003f8 ) 80003d8: 2200 movs r2, #0 80003da: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 80003dc: 4b06 ldr r3, [pc, #24] @ (80003f8 ) 80003de: 2200 movs r2, #0 80003e0: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart2) != HAL_OK) 80003e2: 4805 ldr r0, [pc, #20] @ (80003f8 ) 80003e4: f002 fb22 bl 8002a2c 80003e8: 4603 mov r3, r0 80003ea: 2b00 cmp r3, #0 80003ec: d001 beq.n 80003f2 { Error_Handler(); 80003ee: f000 f8af bl 8000550 } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 80003f2: bf00 nop 80003f4: bd80 pop {r7, pc} 80003f6: bf00 nop 80003f8: 200000fc .word 0x200000fc 80003fc: 40004400 .word 0x40004400 08000400 : * @brief USART3 Initialization Function * @param None * @retval None */ static void MX_USART3_UART_Init(void) { 8000400: b580 push {r7, lr} 8000402: af00 add r7, sp, #0 /* USER CODE END USART3_Init 0 */ /* USER CODE BEGIN USART3_Init 1 */ /* USER CODE END USART3_Init 1 */ huart3.Instance = USART3; 8000404: 4b11 ldr r3, [pc, #68] @ (800044c ) 8000406: 4a12 ldr r2, [pc, #72] @ (8000450 ) 8000408: 601a str r2, [r3, #0] huart3.Init.BaudRate = 115200; 800040a: 4b10 ldr r3, [pc, #64] @ (800044c ) 800040c: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8000410: 605a str r2, [r3, #4] huart3.Init.WordLength = UART_WORDLENGTH_8B; 8000412: 4b0e ldr r3, [pc, #56] @ (800044c ) 8000414: 2200 movs r2, #0 8000416: 609a str r2, [r3, #8] huart3.Init.StopBits = UART_STOPBITS_1; 8000418: 4b0c ldr r3, [pc, #48] @ (800044c ) 800041a: 2200 movs r2, #0 800041c: 60da str r2, [r3, #12] huart3.Init.Parity = UART_PARITY_NONE; 800041e: 4b0b ldr r3, [pc, #44] @ (800044c ) 8000420: 2200 movs r2, #0 8000422: 611a str r2, [r3, #16] huart3.Init.Mode = UART_MODE_TX_RX; 8000424: 4b09 ldr r3, [pc, #36] @ (800044c ) 8000426: 220c movs r2, #12 8000428: 615a str r2, [r3, #20] huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800042a: 4b08 ldr r3, [pc, #32] @ (800044c ) 800042c: 2200 movs r2, #0 800042e: 619a str r2, [r3, #24] huart3.Init.OverSampling = UART_OVERSAMPLING_16; 8000430: 4b06 ldr r3, [pc, #24] @ (800044c ) 8000432: 2200 movs r2, #0 8000434: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart3) != HAL_OK) 8000436: 4805 ldr r0, [pc, #20] @ (800044c ) 8000438: f002 faf8 bl 8002a2c 800043c: 4603 mov r3, r0 800043e: 2b00 cmp r3, #0 8000440: d001 beq.n 8000446 { Error_Handler(); 8000442: f000 f885 bl 8000550 } /* USER CODE BEGIN USART3_Init 2 */ /* USER CODE END USART3_Init 2 */ } 8000446: bf00 nop 8000448: bd80 pop {r7, pc} 800044a: bf00 nop 800044c: 20000144 .word 0x20000144 8000450: 40004800 .word 0x40004800 08000454 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8000454: b580 push {r7, lr} 8000456: b08a sub sp, #40 @ 0x28 8000458: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 800045a: f107 0318 add.w r3, r7, #24 800045e: 2200 movs r2, #0 8000460: 601a str r2, [r3, #0] 8000462: 605a str r2, [r3, #4] 8000464: 609a str r2, [r3, #8] 8000466: 60da str r2, [r3, #12] /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOE_CLK_ENABLE(); 8000468: 4b35 ldr r3, [pc, #212] @ (8000540 ) 800046a: 699b ldr r3, [r3, #24] 800046c: 4a34 ldr r2, [pc, #208] @ (8000540 ) 800046e: f043 0340 orr.w r3, r3, #64 @ 0x40 8000472: 6193 str r3, [r2, #24] 8000474: 4b32 ldr r3, [pc, #200] @ (8000540 ) 8000476: 699b ldr r3, [r3, #24] 8000478: f003 0340 and.w r3, r3, #64 @ 0x40 800047c: 617b str r3, [r7, #20] 800047e: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000480: 4b2f ldr r3, [pc, #188] @ (8000540 ) 8000482: 699b ldr r3, [r3, #24] 8000484: 4a2e ldr r2, [pc, #184] @ (8000540 ) 8000486: f043 0304 orr.w r3, r3, #4 800048a: 6193 str r3, [r2, #24] 800048c: 4b2c ldr r3, [pc, #176] @ (8000540 ) 800048e: 699b ldr r3, [r3, #24] 8000490: f003 0304 and.w r3, r3, #4 8000494: 613b str r3, [r7, #16] 8000496: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); 8000498: 4b29 ldr r3, [pc, #164] @ (8000540 ) 800049a: 699b ldr r3, [r3, #24] 800049c: 4a28 ldr r2, [pc, #160] @ (8000540 ) 800049e: f043 0310 orr.w r3, r3, #16 80004a2: 6193 str r3, [r2, #24] 80004a4: 4b26 ldr r3, [pc, #152] @ (8000540 ) 80004a6: 699b ldr r3, [r3, #24] 80004a8: f003 0310 and.w r3, r3, #16 80004ac: 60fb str r3, [r7, #12] 80004ae: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOB_CLK_ENABLE(); 80004b0: 4b23 ldr r3, [pc, #140] @ (8000540 ) 80004b2: 699b ldr r3, [r3, #24] 80004b4: 4a22 ldr r2, [pc, #136] @ (8000540 ) 80004b6: f043 0308 orr.w r3, r3, #8 80004ba: 6193 str r3, [r2, #24] 80004bc: 4b20 ldr r3, [pc, #128] @ (8000540 ) 80004be: 699b ldr r3, [r3, #24] 80004c0: f003 0308 and.w r3, r3, #8 80004c4: 60bb str r3, [r7, #8] 80004c6: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOD_CLK_ENABLE(); 80004c8: 4b1d ldr r3, [pc, #116] @ (8000540 ) 80004ca: 699b ldr r3, [r3, #24] 80004cc: 4a1c ldr r2, [pc, #112] @ (8000540 ) 80004ce: f043 0320 orr.w r3, r3, #32 80004d2: 6193 str r3, [r2, #24] 80004d4: 4b1a ldr r3, [pc, #104] @ (8000540 ) 80004d6: 699b ldr r3, [r3, #24] 80004d8: f003 0320 and.w r3, r3, #32 80004dc: 607b str r3, [r7, #4] 80004de: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(WiFi_En_GPIO_Port, WiFi_En_Pin, GPIO_PIN_RESET); 80004e0: 2200 movs r2, #0 80004e2: 2110 movs r1, #16 80004e4: 4817 ldr r0, [pc, #92] @ (8000544 ) 80004e6: f000 fece bl 8001286 /*Configure GPIO pin : PE3 */ GPIO_InitStruct.Pin = GPIO_PIN_3; 80004ea: 2308 movs r3, #8 80004ec: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80004ee: 2300 movs r3, #0 80004f0: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 80004f2: 2300 movs r3, #0 80004f4: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 80004f6: f107 0318 add.w r3, r7, #24 80004fa: 4619 mov r1, r3 80004fc: 4812 ldr r0, [pc, #72] @ (8000548 ) 80004fe: f000 fd17 bl 8000f30 /*Configure GPIO pins : EncA_Pin EncB_Pin */ GPIO_InitStruct.Pin = EncA_Pin|EncB_Pin; 8000502: 2303 movs r3, #3 8000504: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8000506: 2300 movs r3, #0 8000508: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 800050a: 2300 movs r3, #0 800050c: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800050e: f107 0318 add.w r3, r7, #24 8000512: 4619 mov r1, r3 8000514: 480d ldr r0, [pc, #52] @ (800054c ) 8000516: f000 fd0b bl 8000f30 /*Configure GPIO pin : WiFi_En_Pin */ GPIO_InitStruct.Pin = WiFi_En_Pin; 800051a: 2310 movs r3, #16 800051c: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800051e: 2301 movs r3, #1 8000520: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000522: 2300 movs r3, #0 8000524: 623b str r3, [r7, #32] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000526: 2302 movs r3, #2 8000528: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(WiFi_En_GPIO_Port, &GPIO_InitStruct); 800052a: f107 0318 add.w r3, r7, #24 800052e: 4619 mov r1, r3 8000530: 4804 ldr r0, [pc, #16] @ (8000544 ) 8000532: f000 fcfd bl 8000f30 /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 8000536: bf00 nop 8000538: 3728 adds r7, #40 @ 0x28 800053a: 46bd mov sp, r7 800053c: bd80 pop {r7, pc} 800053e: bf00 nop 8000540: 40021000 .word 0x40021000 8000544: 40011000 .word 0x40011000 8000548: 40011800 .word 0x40011800 800054c: 40010800 .word 0x40010800 08000550 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8000550: b480 push {r7} 8000552: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8000554: b672 cpsid i } 8000556: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8000558: bf00 nop 800055a: e7fd b.n 8000558 0800055c : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 800055c: b480 push {r7} 800055e: b085 sub sp, #20 8000560: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 8000562: 4b15 ldr r3, [pc, #84] @ (80005b8 ) 8000564: 699b ldr r3, [r3, #24] 8000566: 4a14 ldr r2, [pc, #80] @ (80005b8 ) 8000568: f043 0301 orr.w r3, r3, #1 800056c: 6193 str r3, [r2, #24] 800056e: 4b12 ldr r3, [pc, #72] @ (80005b8 ) 8000570: 699b ldr r3, [r3, #24] 8000572: f003 0301 and.w r3, r3, #1 8000576: 60bb str r3, [r7, #8] 8000578: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 800057a: 4b0f ldr r3, [pc, #60] @ (80005b8 ) 800057c: 69db ldr r3, [r3, #28] 800057e: 4a0e ldr r2, [pc, #56] @ (80005b8 ) 8000580: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8000584: 61d3 str r3, [r2, #28] 8000586: 4b0c ldr r3, [pc, #48] @ (80005b8 ) 8000588: 69db ldr r3, [r3, #28] 800058a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800058e: 607b str r3, [r7, #4] 8000590: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 8000592: 4b0a ldr r3, [pc, #40] @ (80005bc ) 8000594: 685b ldr r3, [r3, #4] 8000596: 60fb str r3, [r7, #12] 8000598: 68fb ldr r3, [r7, #12] 800059a: f023 63e0 bic.w r3, r3, #117440512 @ 0x7000000 800059e: 60fb str r3, [r7, #12] 80005a0: 68fb ldr r3, [r7, #12] 80005a2: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 80005a6: 60fb str r3, [r7, #12] 80005a8: 4a04 ldr r2, [pc, #16] @ (80005bc ) 80005aa: 68fb ldr r3, [r7, #12] 80005ac: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 80005ae: bf00 nop 80005b0: 3714 adds r7, #20 80005b2: 46bd mov sp, r7 80005b4: bc80 pop {r7} 80005b6: 4770 bx lr 80005b8: 40021000 .word 0x40021000 80005bc: 40010000 .word 0x40010000 080005c0 : * This function configures the hardware resources used in this example * @param hcrc: CRC handle pointer * @retval None */ void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc) { 80005c0: b480 push {r7} 80005c2: b085 sub sp, #20 80005c4: af00 add r7, sp, #0 80005c6: 6078 str r0, [r7, #4] if(hcrc->Instance==CRC) 80005c8: 687b ldr r3, [r7, #4] 80005ca: 681b ldr r3, [r3, #0] 80005cc: 4a09 ldr r2, [pc, #36] @ (80005f4 ) 80005ce: 4293 cmp r3, r2 80005d0: d10b bne.n 80005ea { /* USER CODE BEGIN CRC_MspInit 0 */ /* USER CODE END CRC_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_CRC_CLK_ENABLE(); 80005d2: 4b09 ldr r3, [pc, #36] @ (80005f8 ) 80005d4: 695b ldr r3, [r3, #20] 80005d6: 4a08 ldr r2, [pc, #32] @ (80005f8 ) 80005d8: f043 0340 orr.w r3, r3, #64 @ 0x40 80005dc: 6153 str r3, [r2, #20] 80005de: 4b06 ldr r3, [pc, #24] @ (80005f8 ) 80005e0: 695b ldr r3, [r3, #20] 80005e2: f003 0340 and.w r3, r3, #64 @ 0x40 80005e6: 60fb str r3, [r7, #12] 80005e8: 68fb ldr r3, [r7, #12] /* USER CODE END CRC_MspInit 1 */ } } 80005ea: bf00 nop 80005ec: 3714 adds r7, #20 80005ee: 46bd mov sp, r7 80005f0: bc80 pop {r7} 80005f2: 4770 bx lr 80005f4: 40023000 .word 0x40023000 80005f8: 40021000 .word 0x40021000 080005fc : * This function configures the hardware resources used in this example * @param hsd: SD handle pointer * @retval None */ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) { 80005fc: b580 push {r7, lr} 80005fe: b08a sub sp, #40 @ 0x28 8000600: af00 add r7, sp, #0 8000602: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000604: f107 0318 add.w r3, r7, #24 8000608: 2200 movs r2, #0 800060a: 601a str r2, [r3, #0] 800060c: 605a str r2, [r3, #4] 800060e: 609a str r2, [r3, #8] 8000610: 60da str r2, [r3, #12] if(hsd->Instance==SDIO) 8000612: 687b ldr r3, [r7, #4] 8000614: 681b ldr r3, [r3, #0] 8000616: 4a22 ldr r2, [pc, #136] @ (80006a0 ) 8000618: 4293 cmp r3, r2 800061a: d13c bne.n 8000696 { /* USER CODE BEGIN SDIO_MspInit 0 */ /* USER CODE END SDIO_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SDIO_CLK_ENABLE(); 800061c: 4b21 ldr r3, [pc, #132] @ (80006a4 ) 800061e: 695b ldr r3, [r3, #20] 8000620: 4a20 ldr r2, [pc, #128] @ (80006a4 ) 8000622: f443 6380 orr.w r3, r3, #1024 @ 0x400 8000626: 6153 str r3, [r2, #20] 8000628: 4b1e ldr r3, [pc, #120] @ (80006a4 ) 800062a: 695b ldr r3, [r3, #20] 800062c: f403 6380 and.w r3, r3, #1024 @ 0x400 8000630: 617b str r3, [r7, #20] 8000632: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOC_CLK_ENABLE(); 8000634: 4b1b ldr r3, [pc, #108] @ (80006a4 ) 8000636: 699b ldr r3, [r3, #24] 8000638: 4a1a ldr r2, [pc, #104] @ (80006a4 ) 800063a: f043 0310 orr.w r3, r3, #16 800063e: 6193 str r3, [r2, #24] 8000640: 4b18 ldr r3, [pc, #96] @ (80006a4 ) 8000642: 699b ldr r3, [r3, #24] 8000644: f003 0310 and.w r3, r3, #16 8000648: 613b str r3, [r7, #16] 800064a: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOD_CLK_ENABLE(); 800064c: 4b15 ldr r3, [pc, #84] @ (80006a4 ) 800064e: 699b ldr r3, [r3, #24] 8000650: 4a14 ldr r2, [pc, #80] @ (80006a4 ) 8000652: f043 0320 orr.w r3, r3, #32 8000656: 6193 str r3, [r2, #24] 8000658: 4b12 ldr r3, [pc, #72] @ (80006a4 ) 800065a: 699b ldr r3, [r3, #24] 800065c: f003 0320 and.w r3, r3, #32 8000660: 60fb str r3, [r7, #12] 8000662: 68fb ldr r3, [r7, #12] /**SDIO GPIO Configuration PC8 ------> SDIO_D0 PC12 ------> SDIO_CK PD2 ------> SDIO_CMD */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_12; 8000664: f44f 5388 mov.w r3, #4352 @ 0x1100 8000668: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800066a: 2302 movs r3, #2 800066c: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800066e: 2303 movs r3, #3 8000670: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8000672: f107 0318 add.w r3, r7, #24 8000676: 4619 mov r1, r3 8000678: 480b ldr r0, [pc, #44] @ (80006a8 ) 800067a: f000 fc59 bl 8000f30 GPIO_InitStruct.Pin = GPIO_PIN_2; 800067e: 2304 movs r3, #4 8000680: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000682: 2302 movs r3, #2 8000684: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8000686: 2303 movs r3, #3 8000688: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800068a: f107 0318 add.w r3, r7, #24 800068e: 4619 mov r1, r3 8000690: 4806 ldr r0, [pc, #24] @ (80006ac ) 8000692: f000 fc4d bl 8000f30 /* USER CODE END SDIO_MspInit 1 */ } } 8000696: bf00 nop 8000698: 3728 adds r7, #40 @ 0x28 800069a: 46bd mov sp, r7 800069c: bd80 pop {r7, pc} 800069e: bf00 nop 80006a0: 40018000 .word 0x40018000 80006a4: 40021000 .word 0x40021000 80006a8: 40011000 .word 0x40011000 80006ac: 40011400 .word 0x40011400 080006b0 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 80006b0: b580 push {r7, lr} 80006b2: b08c sub sp, #48 @ 0x30 80006b4: af00 add r7, sp, #0 80006b6: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80006b8: f107 0320 add.w r3, r7, #32 80006bc: 2200 movs r2, #0 80006be: 601a str r2, [r3, #0] 80006c0: 605a str r2, [r3, #4] 80006c2: 609a str r2, [r3, #8] 80006c4: 60da str r2, [r3, #12] if(huart->Instance==USART1) 80006c6: 687b ldr r3, [r7, #4] 80006c8: 681b ldr r3, [r3, #0] 80006ca: 4a5f ldr r2, [pc, #380] @ (8000848 ) 80006cc: 4293 cmp r3, r2 80006ce: d13a bne.n 8000746 { /* USER CODE BEGIN USART1_MspInit 0 */ /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); 80006d0: 4b5e ldr r3, [pc, #376] @ (800084c ) 80006d2: 699b ldr r3, [r3, #24] 80006d4: 4a5d ldr r2, [pc, #372] @ (800084c ) 80006d6: f443 4380 orr.w r3, r3, #16384 @ 0x4000 80006da: 6193 str r3, [r2, #24] 80006dc: 4b5b ldr r3, [pc, #364] @ (800084c ) 80006de: 699b ldr r3, [r3, #24] 80006e0: f403 4380 and.w r3, r3, #16384 @ 0x4000 80006e4: 61fb str r3, [r7, #28] 80006e6: 69fb ldr r3, [r7, #28] __HAL_RCC_GPIOA_CLK_ENABLE(); 80006e8: 4b58 ldr r3, [pc, #352] @ (800084c ) 80006ea: 699b ldr r3, [r3, #24] 80006ec: 4a57 ldr r2, [pc, #348] @ (800084c ) 80006ee: f043 0304 orr.w r3, r3, #4 80006f2: 6193 str r3, [r2, #24] 80006f4: 4b55 ldr r3, [pc, #340] @ (800084c ) 80006f6: 699b ldr r3, [r3, #24] 80006f8: f003 0304 and.w r3, r3, #4 80006fc: 61bb str r3, [r7, #24] 80006fe: 69bb ldr r3, [r7, #24] /**USART1 GPIO Configuration PA9 ------> USART1_TX PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9; 8000700: f44f 7300 mov.w r3, #512 @ 0x200 8000704: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000706: 2302 movs r3, #2 8000708: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800070a: 2303 movs r3, #3 800070c: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800070e: f107 0320 add.w r3, r7, #32 8000712: 4619 mov r1, r3 8000714: 484e ldr r0, [pc, #312] @ (8000850 ) 8000716: f000 fc0b bl 8000f30 GPIO_InitStruct.Pin = GPIO_PIN_10; 800071a: f44f 6380 mov.w r3, #1024 @ 0x400 800071e: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8000720: 2300 movs r3, #0 8000722: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Pull = GPIO_PULLUP; 8000724: 2301 movs r3, #1 8000726: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000728: f107 0320 add.w r3, r7, #32 800072c: 4619 mov r1, r3 800072e: 4848 ldr r0, [pc, #288] @ (8000850 ) 8000730: f000 fbfe bl 8000f30 /* USART1 interrupt Init */ HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); 8000734: 2200 movs r2, #0 8000736: 2100 movs r1, #0 8000738: 2025 movs r0, #37 @ 0x25 800073a: f000 fa64 bl 8000c06 HAL_NVIC_EnableIRQ(USART1_IRQn); 800073e: 2025 movs r0, #37 @ 0x25 8000740: f000 fa7d bl 8000c3e /* USER CODE BEGIN USART3_MspInit 1 */ /* USER CODE END USART3_MspInit 1 */ } } 8000744: e07c b.n 8000840 else if(huart->Instance==USART2) 8000746: 687b ldr r3, [r7, #4] 8000748: 681b ldr r3, [r3, #0] 800074a: 4a42 ldr r2, [pc, #264] @ (8000854 ) 800074c: 4293 cmp r3, r2 800074e: d138 bne.n 80007c2 __HAL_RCC_USART2_CLK_ENABLE(); 8000750: 4b3e ldr r3, [pc, #248] @ (800084c ) 8000752: 69db ldr r3, [r3, #28] 8000754: 4a3d ldr r2, [pc, #244] @ (800084c ) 8000756: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800075a: 61d3 str r3, [r2, #28] 800075c: 4b3b ldr r3, [pc, #236] @ (800084c ) 800075e: 69db ldr r3, [r3, #28] 8000760: f403 3300 and.w r3, r3, #131072 @ 0x20000 8000764: 617b str r3, [r7, #20] 8000766: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000768: 4b38 ldr r3, [pc, #224] @ (800084c ) 800076a: 699b ldr r3, [r3, #24] 800076c: 4a37 ldr r2, [pc, #220] @ (800084c ) 800076e: f043 0304 orr.w r3, r3, #4 8000772: 6193 str r3, [r2, #24] 8000774: 4b35 ldr r3, [pc, #212] @ (800084c ) 8000776: 699b ldr r3, [r3, #24] 8000778: f003 0304 and.w r3, r3, #4 800077c: 613b str r3, [r7, #16] 800077e: 693b ldr r3, [r7, #16] GPIO_InitStruct.Pin = GPIO_PIN_2; 8000780: 2304 movs r3, #4 8000782: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000784: 2302 movs r3, #2 8000786: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8000788: 2303 movs r3, #3 800078a: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800078c: f107 0320 add.w r3, r7, #32 8000790: 4619 mov r1, r3 8000792: 482f ldr r0, [pc, #188] @ (8000850 ) 8000794: f000 fbcc bl 8000f30 GPIO_InitStruct.Pin = GPIO_PIN_3; 8000798: 2308 movs r3, #8 800079a: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800079c: 2300 movs r3, #0 800079e: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Pull = GPIO_PULLUP; 80007a0: 2301 movs r3, #1 80007a2: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80007a4: f107 0320 add.w r3, r7, #32 80007a8: 4619 mov r1, r3 80007aa: 4829 ldr r0, [pc, #164] @ (8000850 ) 80007ac: f000 fbc0 bl 8000f30 HAL_NVIC_SetPriority(USART2_IRQn, 0, 0); 80007b0: 2200 movs r2, #0 80007b2: 2100 movs r1, #0 80007b4: 2026 movs r0, #38 @ 0x26 80007b6: f000 fa26 bl 8000c06 HAL_NVIC_EnableIRQ(USART2_IRQn); 80007ba: 2026 movs r0, #38 @ 0x26 80007bc: f000 fa3f bl 8000c3e } 80007c0: e03e b.n 8000840 else if(huart->Instance==USART3) 80007c2: 687b ldr r3, [r7, #4] 80007c4: 681b ldr r3, [r3, #0] 80007c6: 4a24 ldr r2, [pc, #144] @ (8000858 ) 80007c8: 4293 cmp r3, r2 80007ca: d139 bne.n 8000840 __HAL_RCC_USART3_CLK_ENABLE(); 80007cc: 4b1f ldr r3, [pc, #124] @ (800084c ) 80007ce: 69db ldr r3, [r3, #28] 80007d0: 4a1e ldr r2, [pc, #120] @ (800084c ) 80007d2: f443 2380 orr.w r3, r3, #262144 @ 0x40000 80007d6: 61d3 str r3, [r2, #28] 80007d8: 4b1c ldr r3, [pc, #112] @ (800084c ) 80007da: 69db ldr r3, [r3, #28] 80007dc: f403 2380 and.w r3, r3, #262144 @ 0x40000 80007e0: 60fb str r3, [r7, #12] 80007e2: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOB_CLK_ENABLE(); 80007e4: 4b19 ldr r3, [pc, #100] @ (800084c ) 80007e6: 699b ldr r3, [r3, #24] 80007e8: 4a18 ldr r2, [pc, #96] @ (800084c ) 80007ea: f043 0308 orr.w r3, r3, #8 80007ee: 6193 str r3, [r2, #24] 80007f0: 4b16 ldr r3, [pc, #88] @ (800084c ) 80007f2: 699b ldr r3, [r3, #24] 80007f4: f003 0308 and.w r3, r3, #8 80007f8: 60bb str r3, [r7, #8] 80007fa: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = GPIO_PIN_10; 80007fc: f44f 6380 mov.w r3, #1024 @ 0x400 8000800: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000802: 2302 movs r3, #2 8000804: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8000806: 2303 movs r3, #3 8000808: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800080a: f107 0320 add.w r3, r7, #32 800080e: 4619 mov r1, r3 8000810: 4812 ldr r0, [pc, #72] @ (800085c ) 8000812: f000 fb8d bl 8000f30 GPIO_InitStruct.Pin = GPIO_PIN_11; 8000816: f44f 6300 mov.w r3, #2048 @ 0x800 800081a: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800081c: 2300 movs r3, #0 800081e: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Pull = GPIO_PULLUP; 8000820: 2301 movs r3, #1 8000822: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8000824: f107 0320 add.w r3, r7, #32 8000828: 4619 mov r1, r3 800082a: 480c ldr r0, [pc, #48] @ (800085c ) 800082c: f000 fb80 bl 8000f30 HAL_NVIC_SetPriority(USART3_IRQn, 0, 0); 8000830: 2200 movs r2, #0 8000832: 2100 movs r1, #0 8000834: 2027 movs r0, #39 @ 0x27 8000836: f000 f9e6 bl 8000c06 HAL_NVIC_EnableIRQ(USART3_IRQn); 800083a: 2027 movs r0, #39 @ 0x27 800083c: f000 f9ff bl 8000c3e } 8000840: bf00 nop 8000842: 3730 adds r7, #48 @ 0x30 8000844: 46bd mov sp, r7 8000846: bd80 pop {r7, pc} 8000848: 40013800 .word 0x40013800 800084c: 40021000 .word 0x40021000 8000850: 40010800 .word 0x40010800 8000854: 40004400 .word 0x40004400 8000858: 40004800 .word 0x40004800 800085c: 40010c00 .word 0x40010c00 08000860 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8000860: b480 push {r7} 8000862: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8000864: bf00 nop 8000866: e7fd b.n 8000864 08000868 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8000868: b480 push {r7} 800086a: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 800086c: bf00 nop 800086e: e7fd b.n 800086c 08000870 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8000870: b480 push {r7} 8000872: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8000874: bf00 nop 8000876: e7fd b.n 8000874 08000878 : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 8000878: b480 push {r7} 800087a: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 800087c: bf00 nop 800087e: e7fd b.n 800087c 08000880 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8000880: b480 push {r7} 8000882: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8000884: bf00 nop 8000886: e7fd b.n 8000884 08000888 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8000888: b480 push {r7} 800088a: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 800088c: bf00 nop 800088e: 46bd mov sp, r7 8000890: bc80 pop {r7} 8000892: 4770 bx lr 08000894 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8000894: b480 push {r7} 8000896: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8000898: bf00 nop 800089a: 46bd mov sp, r7 800089c: bc80 pop {r7} 800089e: 4770 bx lr 080008a0 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 80008a0: b480 push {r7} 80008a2: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 80008a4: bf00 nop 80008a6: 46bd mov sp, r7 80008a8: bc80 pop {r7} 80008aa: 4770 bx lr 080008ac : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 80008ac: b580 push {r7, lr} 80008ae: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 80008b0: f000 f892 bl 80009d8 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 80008b4: bf00 nop 80008b6: bd80 pop {r7, pc} 080008b8 : /** * @brief This function handles USART1 global interrupt. */ void USART1_IRQHandler(void) { 80008b8: b580 push {r7, lr} 80008ba: af00 add r7, sp, #0 /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 80008bc: 4802 ldr r0, [pc, #8] @ (80008c8 ) 80008be: f002 f905 bl 8002acc /* USER CODE BEGIN USART1_IRQn 1 */ /* USER CODE END USART1_IRQn 1 */ } 80008c2: bf00 nop 80008c4: bd80 pop {r7, pc} 80008c6: bf00 nop 80008c8: 200000b4 .word 0x200000b4 080008cc : /** * @brief This function handles USART2 global interrupt. */ void USART2_IRQHandler(void) { 80008cc: b580 push {r7, lr} 80008ce: af00 add r7, sp, #0 /* USER CODE BEGIN USART2_IRQn 0 */ /* USER CODE END USART2_IRQn 0 */ HAL_UART_IRQHandler(&huart2); 80008d0: 4802 ldr r0, [pc, #8] @ (80008dc ) 80008d2: f002 f8fb bl 8002acc /* USER CODE BEGIN USART2_IRQn 1 */ /* USER CODE END USART2_IRQn 1 */ } 80008d6: bf00 nop 80008d8: bd80 pop {r7, pc} 80008da: bf00 nop 80008dc: 200000fc .word 0x200000fc 080008e0 : /** * @brief This function handles USART3 global interrupt. */ void USART3_IRQHandler(void) { 80008e0: b580 push {r7, lr} 80008e2: af00 add r7, sp, #0 /* USER CODE BEGIN USART3_IRQn 0 */ /* USER CODE END USART3_IRQn 0 */ HAL_UART_IRQHandler(&huart3); 80008e4: 4802 ldr r0, [pc, #8] @ (80008f0 ) 80008e6: f002 f8f1 bl 8002acc /* USER CODE BEGIN USART3_IRQn 1 */ /* USER CODE END USART3_IRQn 1 */ } 80008ea: bf00 nop 80008ec: bd80 pop {r7, pc} 80008ee: bf00 nop 80008f0: 20000144 .word 0x20000144 080008f4 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 80008f4: b480 push {r7} 80008f6: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 80008f8: bf00 nop 80008fa: 46bd mov sp, r7 80008fc: bc80 pop {r7} 80008fe: 4770 bx lr 08000900 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Call the clock system initialization function.*/ bl SystemInit 8000900: f7ff fff8 bl 80008f4 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8000904: 480b ldr r0, [pc, #44] @ (8000934 ) ldr r1, =_edata 8000906: 490c ldr r1, [pc, #48] @ (8000938 ) ldr r2, =_sidata 8000908: 4a0c ldr r2, [pc, #48] @ (800093c ) movs r3, #0 800090a: 2300 movs r3, #0 b LoopCopyDataInit 800090c: e002 b.n 8000914 0800090e : CopyDataInit: ldr r4, [r2, r3] 800090e: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8000910: 50c4 str r4, [r0, r3] adds r3, r3, #4 8000912: 3304 adds r3, #4 08000914 : LoopCopyDataInit: adds r4, r0, r3 8000914: 18c4 adds r4, r0, r3 cmp r4, r1 8000916: 428c cmp r4, r1 bcc CopyDataInit 8000918: d3f9 bcc.n 800090e /* Zero fill the bss segment. */ ldr r2, =_sbss 800091a: 4a09 ldr r2, [pc, #36] @ (8000940 ) ldr r4, =_ebss 800091c: 4c09 ldr r4, [pc, #36] @ (8000944 ) movs r3, #0 800091e: 2300 movs r3, #0 b LoopFillZerobss 8000920: e001 b.n 8000926 08000922 : FillZerobss: str r3, [r2] 8000922: 6013 str r3, [r2, #0] adds r2, r2, #4 8000924: 3204 adds r2, #4 08000926 : LoopFillZerobss: cmp r2, r4 8000926: 42a2 cmp r2, r4 bcc FillZerobss 8000928: d3fb bcc.n 8000922 /* Call static constructors */ bl __libc_init_array 800092a: f003 fcd1 bl 80042d0 <__libc_init_array> /* Call the application's entry point.*/ bl main 800092e: f7ff fc79 bl 8000224
bx lr 8000932: 4770 bx lr ldr r0, =_sdata 8000934: 20000000 .word 0x20000000 ldr r1, =_edata 8000938: 2000000c .word 0x2000000c ldr r2, =_sidata 800093c: 08004378 .word 0x08004378 ldr r2, =_sbss 8000940: 2000000c .word 0x2000000c ldr r4, =_ebss 8000944: 200001a4 .word 0x200001a4 08000948 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8000948: e7fe b.n 8000948 ... 0800094c : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 800094c: b580 push {r7, lr} 800094e: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8000950: 4b08 ldr r3, [pc, #32] @ (8000974 ) 8000952: 681b ldr r3, [r3, #0] 8000954: 4a07 ldr r2, [pc, #28] @ (8000974 ) 8000956: f043 0310 orr.w r3, r3, #16 800095a: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 800095c: 2003 movs r0, #3 800095e: f000 f947 bl 8000bf0 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 8000962: 200f movs r0, #15 8000964: f000 f808 bl 8000978 /* Init the low level hardware */ HAL_MspInit(); 8000968: f7ff fdf8 bl 800055c /* Return function status */ return HAL_OK; 800096c: 2300 movs r3, #0 } 800096e: 4618 mov r0, r3 8000970: bd80 pop {r7, pc} 8000972: bf00 nop 8000974: 40022000 .word 0x40022000 08000978 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8000978: b580 push {r7, lr} 800097a: b082 sub sp, #8 800097c: af00 add r7, sp, #0 800097e: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8000980: 4b12 ldr r3, [pc, #72] @ (80009cc ) 8000982: 681a ldr r2, [r3, #0] 8000984: 4b12 ldr r3, [pc, #72] @ (80009d0 ) 8000986: 781b ldrb r3, [r3, #0] 8000988: 4619 mov r1, r3 800098a: f44f 737a mov.w r3, #1000 @ 0x3e8 800098e: fbb3 f3f1 udiv r3, r3, r1 8000992: fbb2 f3f3 udiv r3, r2, r3 8000996: 4618 mov r0, r3 8000998: f000 f95f bl 8000c5a 800099c: 4603 mov r3, r0 800099e: 2b00 cmp r3, #0 80009a0: d001 beq.n 80009a6 { return HAL_ERROR; 80009a2: 2301 movs r3, #1 80009a4: e00e b.n 80009c4 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 80009a6: 687b ldr r3, [r7, #4] 80009a8: 2b0f cmp r3, #15 80009aa: d80a bhi.n 80009c2 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 80009ac: 2200 movs r2, #0 80009ae: 6879 ldr r1, [r7, #4] 80009b0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80009b4: f000 f927 bl 8000c06 uwTickPrio = TickPriority; 80009b8: 4a06 ldr r2, [pc, #24] @ (80009d4 ) 80009ba: 687b ldr r3, [r7, #4] 80009bc: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 80009be: 2300 movs r3, #0 80009c0: e000 b.n 80009c4 return HAL_ERROR; 80009c2: 2301 movs r3, #1 } 80009c4: 4618 mov r0, r3 80009c6: 3708 adds r7, #8 80009c8: 46bd mov sp, r7 80009ca: bd80 pop {r7, pc} 80009cc: 20000000 .word 0x20000000 80009d0: 20000008 .word 0x20000008 80009d4: 20000004 .word 0x20000004 080009d8 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 80009d8: b480 push {r7} 80009da: af00 add r7, sp, #0 uwTick += uwTickFreq; 80009dc: 4b05 ldr r3, [pc, #20] @ (80009f4 ) 80009de: 781b ldrb r3, [r3, #0] 80009e0: 461a mov r2, r3 80009e2: 4b05 ldr r3, [pc, #20] @ (80009f8 ) 80009e4: 681b ldr r3, [r3, #0] 80009e6: 4413 add r3, r2 80009e8: 4a03 ldr r2, [pc, #12] @ (80009f8 ) 80009ea: 6013 str r3, [r2, #0] } 80009ec: bf00 nop 80009ee: 46bd mov sp, r7 80009f0: bc80 pop {r7} 80009f2: 4770 bx lr 80009f4: 20000008 .word 0x20000008 80009f8: 2000018c .word 0x2000018c 080009fc : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 80009fc: b480 push {r7} 80009fe: af00 add r7, sp, #0 return uwTick; 8000a00: 4b02 ldr r3, [pc, #8] @ (8000a0c ) 8000a02: 681b ldr r3, [r3, #0] } 8000a04: 4618 mov r0, r3 8000a06: 46bd mov sp, r7 8000a08: bc80 pop {r7} 8000a0a: 4770 bx lr 8000a0c: 2000018c .word 0x2000018c 08000a10 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8000a10: b580 push {r7, lr} 8000a12: b084 sub sp, #16 8000a14: af00 add r7, sp, #0 8000a16: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8000a18: f7ff fff0 bl 80009fc 8000a1c: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 8000a1e: 687b ldr r3, [r7, #4] 8000a20: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 8000a22: 68fb ldr r3, [r7, #12] 8000a24: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8000a28: d005 beq.n 8000a36 { wait += (uint32_t)(uwTickFreq); 8000a2a: 4b0a ldr r3, [pc, #40] @ (8000a54 ) 8000a2c: 781b ldrb r3, [r3, #0] 8000a2e: 461a mov r2, r3 8000a30: 68fb ldr r3, [r7, #12] 8000a32: 4413 add r3, r2 8000a34: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 8000a36: bf00 nop 8000a38: f7ff ffe0 bl 80009fc 8000a3c: 4602 mov r2, r0 8000a3e: 68bb ldr r3, [r7, #8] 8000a40: 1ad3 subs r3, r2, r3 8000a42: 68fa ldr r2, [r7, #12] 8000a44: 429a cmp r2, r3 8000a46: d8f7 bhi.n 8000a38 { } } 8000a48: bf00 nop 8000a4a: bf00 nop 8000a4c: 3710 adds r7, #16 8000a4e: 46bd mov sp, r7 8000a50: bd80 pop {r7, pc} 8000a52: bf00 nop 8000a54: 20000008 .word 0x20000008 08000a58 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8000a58: b480 push {r7} 8000a5a: b085 sub sp, #20 8000a5c: af00 add r7, sp, #0 8000a5e: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8000a60: 687b ldr r3, [r7, #4] 8000a62: f003 0307 and.w r3, r3, #7 8000a66: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8000a68: 4b0c ldr r3, [pc, #48] @ (8000a9c <__NVIC_SetPriorityGrouping+0x44>) 8000a6a: 68db ldr r3, [r3, #12] 8000a6c: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8000a6e: 68ba ldr r2, [r7, #8] 8000a70: f64f 03ff movw r3, #63743 @ 0xf8ff 8000a74: 4013 ands r3, r2 8000a76: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8000a78: 68fb ldr r3, [r7, #12] 8000a7a: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8000a7c: 68bb ldr r3, [r7, #8] 8000a7e: 4313 orrs r3, r2 reg_value = (reg_value | 8000a80: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 8000a84: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8000a88: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8000a8a: 4a04 ldr r2, [pc, #16] @ (8000a9c <__NVIC_SetPriorityGrouping+0x44>) 8000a8c: 68bb ldr r3, [r7, #8] 8000a8e: 60d3 str r3, [r2, #12] } 8000a90: bf00 nop 8000a92: 3714 adds r7, #20 8000a94: 46bd mov sp, r7 8000a96: bc80 pop {r7} 8000a98: 4770 bx lr 8000a9a: bf00 nop 8000a9c: e000ed00 .word 0xe000ed00 08000aa0 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8000aa0: b480 push {r7} 8000aa2: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8000aa4: 4b04 ldr r3, [pc, #16] @ (8000ab8 <__NVIC_GetPriorityGrouping+0x18>) 8000aa6: 68db ldr r3, [r3, #12] 8000aa8: 0a1b lsrs r3, r3, #8 8000aaa: f003 0307 and.w r3, r3, #7 } 8000aae: 4618 mov r0, r3 8000ab0: 46bd mov sp, r7 8000ab2: bc80 pop {r7} 8000ab4: 4770 bx lr 8000ab6: bf00 nop 8000ab8: e000ed00 .word 0xe000ed00 08000abc <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 8000abc: b480 push {r7} 8000abe: b083 sub sp, #12 8000ac0: af00 add r7, sp, #0 8000ac2: 4603 mov r3, r0 8000ac4: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8000ac6: f997 3007 ldrsb.w r3, [r7, #7] 8000aca: 2b00 cmp r3, #0 8000acc: db0b blt.n 8000ae6 <__NVIC_EnableIRQ+0x2a> { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8000ace: 79fb ldrb r3, [r7, #7] 8000ad0: f003 021f and.w r2, r3, #31 8000ad4: 4906 ldr r1, [pc, #24] @ (8000af0 <__NVIC_EnableIRQ+0x34>) 8000ad6: f997 3007 ldrsb.w r3, [r7, #7] 8000ada: 095b lsrs r3, r3, #5 8000adc: 2001 movs r0, #1 8000ade: fa00 f202 lsl.w r2, r0, r2 8000ae2: f841 2023 str.w r2, [r1, r3, lsl #2] } } 8000ae6: bf00 nop 8000ae8: 370c adds r7, #12 8000aea: 46bd mov sp, r7 8000aec: bc80 pop {r7} 8000aee: 4770 bx lr 8000af0: e000e100 .word 0xe000e100 08000af4 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8000af4: b480 push {r7} 8000af6: b083 sub sp, #12 8000af8: af00 add r7, sp, #0 8000afa: 4603 mov r3, r0 8000afc: 6039 str r1, [r7, #0] 8000afe: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8000b00: f997 3007 ldrsb.w r3, [r7, #7] 8000b04: 2b00 cmp r3, #0 8000b06: db0a blt.n 8000b1e <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8000b08: 683b ldr r3, [r7, #0] 8000b0a: b2da uxtb r2, r3 8000b0c: 490c ldr r1, [pc, #48] @ (8000b40 <__NVIC_SetPriority+0x4c>) 8000b0e: f997 3007 ldrsb.w r3, [r7, #7] 8000b12: 0112 lsls r2, r2, #4 8000b14: b2d2 uxtb r2, r2 8000b16: 440b add r3, r1 8000b18: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8000b1c: e00a b.n 8000b34 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8000b1e: 683b ldr r3, [r7, #0] 8000b20: b2da uxtb r2, r3 8000b22: 4908 ldr r1, [pc, #32] @ (8000b44 <__NVIC_SetPriority+0x50>) 8000b24: 79fb ldrb r3, [r7, #7] 8000b26: f003 030f and.w r3, r3, #15 8000b2a: 3b04 subs r3, #4 8000b2c: 0112 lsls r2, r2, #4 8000b2e: b2d2 uxtb r2, r2 8000b30: 440b add r3, r1 8000b32: 761a strb r2, [r3, #24] } 8000b34: bf00 nop 8000b36: 370c adds r7, #12 8000b38: 46bd mov sp, r7 8000b3a: bc80 pop {r7} 8000b3c: 4770 bx lr 8000b3e: bf00 nop 8000b40: e000e100 .word 0xe000e100 8000b44: e000ed00 .word 0xe000ed00 08000b48 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 8000b48: b480 push {r7} 8000b4a: b089 sub sp, #36 @ 0x24 8000b4c: af00 add r7, sp, #0 8000b4e: 60f8 str r0, [r7, #12] 8000b50: 60b9 str r1, [r7, #8] 8000b52: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8000b54: 68fb ldr r3, [r7, #12] 8000b56: f003 0307 and.w r3, r3, #7 8000b5a: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8000b5c: 69fb ldr r3, [r7, #28] 8000b5e: f1c3 0307 rsb r3, r3, #7 8000b62: 2b04 cmp r3, #4 8000b64: bf28 it cs 8000b66: 2304 movcs r3, #4 8000b68: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8000b6a: 69fb ldr r3, [r7, #28] 8000b6c: 3304 adds r3, #4 8000b6e: 2b06 cmp r3, #6 8000b70: d902 bls.n 8000b78 8000b72: 69fb ldr r3, [r7, #28] 8000b74: 3b03 subs r3, #3 8000b76: e000 b.n 8000b7a 8000b78: 2300 movs r3, #0 8000b7a: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8000b7c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8000b80: 69bb ldr r3, [r7, #24] 8000b82: fa02 f303 lsl.w r3, r2, r3 8000b86: 43da mvns r2, r3 8000b88: 68bb ldr r3, [r7, #8] 8000b8a: 401a ands r2, r3 8000b8c: 697b ldr r3, [r7, #20] 8000b8e: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8000b90: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8000b94: 697b ldr r3, [r7, #20] 8000b96: fa01 f303 lsl.w r3, r1, r3 8000b9a: 43d9 mvns r1, r3 8000b9c: 687b ldr r3, [r7, #4] 8000b9e: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8000ba0: 4313 orrs r3, r2 ); } 8000ba2: 4618 mov r0, r3 8000ba4: 3724 adds r7, #36 @ 0x24 8000ba6: 46bd mov sp, r7 8000ba8: bc80 pop {r7} 8000baa: 4770 bx lr 08000bac : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8000bac: b580 push {r7, lr} 8000bae: b082 sub sp, #8 8000bb0: af00 add r7, sp, #0 8000bb2: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8000bb4: 687b ldr r3, [r7, #4] 8000bb6: 3b01 subs r3, #1 8000bb8: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8000bbc: d301 bcc.n 8000bc2 { return (1UL); /* Reload value impossible */ 8000bbe: 2301 movs r3, #1 8000bc0: e00f b.n 8000be2 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8000bc2: 4a0a ldr r2, [pc, #40] @ (8000bec ) 8000bc4: 687b ldr r3, [r7, #4] 8000bc6: 3b01 subs r3, #1 8000bc8: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8000bca: 210f movs r1, #15 8000bcc: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8000bd0: f7ff ff90 bl 8000af4 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8000bd4: 4b05 ldr r3, [pc, #20] @ (8000bec ) 8000bd6: 2200 movs r2, #0 8000bd8: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8000bda: 4b04 ldr r3, [pc, #16] @ (8000bec ) 8000bdc: 2207 movs r2, #7 8000bde: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8000be0: 2300 movs r3, #0 } 8000be2: 4618 mov r0, r3 8000be4: 3708 adds r7, #8 8000be6: 46bd mov sp, r7 8000be8: bd80 pop {r7, pc} 8000bea: bf00 nop 8000bec: e000e010 .word 0xe000e010 08000bf0 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8000bf0: b580 push {r7, lr} 8000bf2: b082 sub sp, #8 8000bf4: af00 add r7, sp, #0 8000bf6: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8000bf8: 6878 ldr r0, [r7, #4] 8000bfa: f7ff ff2d bl 8000a58 <__NVIC_SetPriorityGrouping> } 8000bfe: bf00 nop 8000c00: 3708 adds r7, #8 8000c02: 46bd mov sp, r7 8000c04: bd80 pop {r7, pc} 08000c06 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8000c06: b580 push {r7, lr} 8000c08: b086 sub sp, #24 8000c0a: af00 add r7, sp, #0 8000c0c: 4603 mov r3, r0 8000c0e: 60b9 str r1, [r7, #8] 8000c10: 607a str r2, [r7, #4] 8000c12: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8000c14: 2300 movs r3, #0 8000c16: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8000c18: f7ff ff42 bl 8000aa0 <__NVIC_GetPriorityGrouping> 8000c1c: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8000c1e: 687a ldr r2, [r7, #4] 8000c20: 68b9 ldr r1, [r7, #8] 8000c22: 6978 ldr r0, [r7, #20] 8000c24: f7ff ff90 bl 8000b48 8000c28: 4602 mov r2, r0 8000c2a: f997 300f ldrsb.w r3, [r7, #15] 8000c2e: 4611 mov r1, r2 8000c30: 4618 mov r0, r3 8000c32: f7ff ff5f bl 8000af4 <__NVIC_SetPriority> } 8000c36: bf00 nop 8000c38: 3718 adds r7, #24 8000c3a: 46bd mov sp, r7 8000c3c: bd80 pop {r7, pc} 08000c3e : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8000c3e: b580 push {r7, lr} 8000c40: b082 sub sp, #8 8000c42: af00 add r7, sp, #0 8000c44: 4603 mov r3, r0 8000c46: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8000c48: f997 3007 ldrsb.w r3, [r7, #7] 8000c4c: 4618 mov r0, r3 8000c4e: f7ff ff35 bl 8000abc <__NVIC_EnableIRQ> } 8000c52: bf00 nop 8000c54: 3708 adds r7, #8 8000c56: 46bd mov sp, r7 8000c58: bd80 pop {r7, pc} 08000c5a : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8000c5a: b580 push {r7, lr} 8000c5c: b082 sub sp, #8 8000c5e: af00 add r7, sp, #0 8000c60: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8000c62: 6878 ldr r0, [r7, #4] 8000c64: f7ff ffa2 bl 8000bac 8000c68: 4603 mov r3, r0 } 8000c6a: 4618 mov r0, r3 8000c6c: 3708 adds r7, #8 8000c6e: 46bd mov sp, r7 8000c70: bd80 pop {r7, pc} 08000c72 : * parameters in the CRC_InitTypeDef and create the associated handle. * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) { 8000c72: b580 push {r7, lr} 8000c74: b082 sub sp, #8 8000c76: af00 add r7, sp, #0 8000c78: 6078 str r0, [r7, #4] /* Check the CRC handle allocation */ if (hcrc == NULL) 8000c7a: 687b ldr r3, [r7, #4] 8000c7c: 2b00 cmp r3, #0 8000c7e: d101 bne.n 8000c84 { return HAL_ERROR; 8000c80: 2301 movs r3, #1 8000c82: e00e b.n 8000ca2 } /* Check the parameters */ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); if (hcrc->State == HAL_CRC_STATE_RESET) 8000c84: 687b ldr r3, [r7, #4] 8000c86: 795b ldrb r3, [r3, #5] 8000c88: b2db uxtb r3, r3 8000c8a: 2b00 cmp r3, #0 8000c8c: d105 bne.n 8000c9a { /* Allocate lock resource and initialize it */ hcrc->Lock = HAL_UNLOCKED; 8000c8e: 687b ldr r3, [r7, #4] 8000c90: 2200 movs r2, #0 8000c92: 711a strb r2, [r3, #4] /* Init the low level hardware */ HAL_CRC_MspInit(hcrc); 8000c94: 6878 ldr r0, [r7, #4] 8000c96: f7ff fc93 bl 80005c0 } /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; 8000c9a: 687b ldr r3, [r7, #4] 8000c9c: 2201 movs r2, #1 8000c9e: 715a strb r2, [r3, #5] /* Return function status */ return HAL_OK; 8000ca0: 2300 movs r3, #0 } 8000ca2: 4618 mov r0, r3 8000ca4: 3708 adds r7, #8 8000ca6: 46bd mov sp, r7 8000ca8: bd80 pop {r7, pc} 08000caa : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 8000caa: b480 push {r7} 8000cac: b085 sub sp, #20 8000cae: af00 add r7, sp, #0 8000cb0: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8000cb2: 2300 movs r3, #0 8000cb4: 73fb strb r3, [r7, #15] if(hdma->State != HAL_DMA_STATE_BUSY) 8000cb6: 687b ldr r3, [r7, #4] 8000cb8: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 8000cbc: b2db uxtb r3, r3 8000cbe: 2b02 cmp r3, #2 8000cc0: d008 beq.n 8000cd4 { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8000cc2: 687b ldr r3, [r7, #4] 8000cc4: 2204 movs r2, #4 8000cc6: 639a str r2, [r3, #56] @ 0x38 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8000cc8: 687b ldr r3, [r7, #4] 8000cca: 2200 movs r2, #0 8000ccc: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 8000cd0: 2301 movs r3, #1 8000cd2: e020 b.n 8000d16 } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8000cd4: 687b ldr r3, [r7, #4] 8000cd6: 681b ldr r3, [r3, #0] 8000cd8: 681a ldr r2, [r3, #0] 8000cda: 687b ldr r3, [r7, #4] 8000cdc: 681b ldr r3, [r3, #0] 8000cde: f022 020e bic.w r2, r2, #14 8000ce2: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 8000ce4: 687b ldr r3, [r7, #4] 8000ce6: 681b ldr r3, [r3, #0] 8000ce8: 681a ldr r2, [r3, #0] 8000cea: 687b ldr r3, [r7, #4] 8000cec: 681b ldr r3, [r3, #0] 8000cee: f022 0201 bic.w r2, r2, #1 8000cf2: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 8000cf4: 687b ldr r3, [r7, #4] 8000cf6: 6c1a ldr r2, [r3, #64] @ 0x40 8000cf8: 687b ldr r3, [r7, #4] 8000cfa: 6bdb ldr r3, [r3, #60] @ 0x3c 8000cfc: 2101 movs r1, #1 8000cfe: fa01 f202 lsl.w r2, r1, r2 8000d02: 605a str r2, [r3, #4] } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8000d04: 687b ldr r3, [r7, #4] 8000d06: 2201 movs r2, #1 8000d08: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8000d0c: 687b ldr r3, [r7, #4] 8000d0e: 2200 movs r2, #0 8000d10: f883 2020 strb.w r2, [r3, #32] return status; 8000d14: 7bfb ldrb r3, [r7, #15] } 8000d16: 4618 mov r0, r3 8000d18: 3714 adds r7, #20 8000d1a: 46bd mov sp, r7 8000d1c: bc80 pop {r7} 8000d1e: 4770 bx lr 08000d20 : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 8000d20: b580 push {r7, lr} 8000d22: b084 sub sp, #16 8000d24: af00 add r7, sp, #0 8000d26: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8000d28: 2300 movs r3, #0 8000d2a: 73fb strb r3, [r7, #15] if(HAL_DMA_STATE_BUSY != hdma->State) 8000d2c: 687b ldr r3, [r7, #4] 8000d2e: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 8000d32: b2db uxtb r3, r3 8000d34: 2b02 cmp r3, #2 8000d36: d005 beq.n 8000d44 { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8000d38: 687b ldr r3, [r7, #4] 8000d3a: 2204 movs r2, #4 8000d3c: 639a str r2, [r3, #56] @ 0x38 status = HAL_ERROR; 8000d3e: 2301 movs r3, #1 8000d40: 73fb strb r3, [r7, #15] 8000d42: e0d6 b.n 8000ef2 } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8000d44: 687b ldr r3, [r7, #4] 8000d46: 681b ldr r3, [r3, #0] 8000d48: 681a ldr r2, [r3, #0] 8000d4a: 687b ldr r3, [r7, #4] 8000d4c: 681b ldr r3, [r3, #0] 8000d4e: f022 020e bic.w r2, r2, #14 8000d52: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 8000d54: 687b ldr r3, [r7, #4] 8000d56: 681b ldr r3, [r3, #0] 8000d58: 681a ldr r2, [r3, #0] 8000d5a: 687b ldr r3, [r7, #4] 8000d5c: 681b ldr r3, [r3, #0] 8000d5e: f022 0201 bic.w r2, r2, #1 8000d62: 601a str r2, [r3, #0] /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); 8000d64: 687b ldr r3, [r7, #4] 8000d66: 681b ldr r3, [r3, #0] 8000d68: 461a mov r2, r3 8000d6a: 4b64 ldr r3, [pc, #400] @ (8000efc ) 8000d6c: 429a cmp r2, r3 8000d6e: d958 bls.n 8000e22 8000d70: 687b ldr r3, [r7, #4] 8000d72: 681b ldr r3, [r3, #0] 8000d74: 4a62 ldr r2, [pc, #392] @ (8000f00 ) 8000d76: 4293 cmp r3, r2 8000d78: d04f beq.n 8000e1a 8000d7a: 687b ldr r3, [r7, #4] 8000d7c: 681b ldr r3, [r3, #0] 8000d7e: 4a61 ldr r2, [pc, #388] @ (8000f04 ) 8000d80: 4293 cmp r3, r2 8000d82: d048 beq.n 8000e16 8000d84: 687b ldr r3, [r7, #4] 8000d86: 681b ldr r3, [r3, #0] 8000d88: 4a5f ldr r2, [pc, #380] @ (8000f08 ) 8000d8a: 4293 cmp r3, r2 8000d8c: d040 beq.n 8000e10 8000d8e: 687b ldr r3, [r7, #4] 8000d90: 681b ldr r3, [r3, #0] 8000d92: 4a5e ldr r2, [pc, #376] @ (8000f0c ) 8000d94: 4293 cmp r3, r2 8000d96: d038 beq.n 8000e0a 8000d98: 687b ldr r3, [r7, #4] 8000d9a: 681b ldr r3, [r3, #0] 8000d9c: 4a5c ldr r2, [pc, #368] @ (8000f10 ) 8000d9e: 4293 cmp r3, r2 8000da0: d030 beq.n 8000e04 8000da2: 687b ldr r3, [r7, #4] 8000da4: 681b ldr r3, [r3, #0] 8000da6: 4a5b ldr r2, [pc, #364] @ (8000f14 ) 8000da8: 4293 cmp r3, r2 8000daa: d028 beq.n 8000dfe 8000dac: 687b ldr r3, [r7, #4] 8000dae: 681b ldr r3, [r3, #0] 8000db0: 4a52 ldr r2, [pc, #328] @ (8000efc ) 8000db2: 4293 cmp r3, r2 8000db4: d020 beq.n 8000df8 8000db6: 687b ldr r3, [r7, #4] 8000db8: 681b ldr r3, [r3, #0] 8000dba: 4a57 ldr r2, [pc, #348] @ (8000f18 ) 8000dbc: 4293 cmp r3, r2 8000dbe: d019 beq.n 8000df4 8000dc0: 687b ldr r3, [r7, #4] 8000dc2: 681b ldr r3, [r3, #0] 8000dc4: 4a55 ldr r2, [pc, #340] @ (8000f1c ) 8000dc6: 4293 cmp r3, r2 8000dc8: d012 beq.n 8000df0 8000dca: 687b ldr r3, [r7, #4] 8000dcc: 681b ldr r3, [r3, #0] 8000dce: 4a54 ldr r2, [pc, #336] @ (8000f20 ) 8000dd0: 4293 cmp r3, r2 8000dd2: d00a beq.n 8000dea 8000dd4: 687b ldr r3, [r7, #4] 8000dd6: 681b ldr r3, [r3, #0] 8000dd8: 4a52 ldr r2, [pc, #328] @ (8000f24 ) 8000dda: 4293 cmp r3, r2 8000ddc: d102 bne.n 8000de4 8000dde: f44f 5380 mov.w r3, #4096 @ 0x1000 8000de2: e01b b.n 8000e1c 8000de4: f44f 3380 mov.w r3, #65536 @ 0x10000 8000de8: e018 b.n 8000e1c 8000dea: f44f 7380 mov.w r3, #256 @ 0x100 8000dee: e015 b.n 8000e1c 8000df0: 2310 movs r3, #16 8000df2: e013 b.n 8000e1c 8000df4: 2301 movs r3, #1 8000df6: e011 b.n 8000e1c 8000df8: f04f 7380 mov.w r3, #16777216 @ 0x1000000 8000dfc: e00e b.n 8000e1c 8000dfe: f44f 1380 mov.w r3, #1048576 @ 0x100000 8000e02: e00b b.n 8000e1c 8000e04: f44f 3380 mov.w r3, #65536 @ 0x10000 8000e08: e008 b.n 8000e1c 8000e0a: f44f 5380 mov.w r3, #4096 @ 0x1000 8000e0e: e005 b.n 8000e1c 8000e10: f44f 7380 mov.w r3, #256 @ 0x100 8000e14: e002 b.n 8000e1c 8000e16: 2310 movs r3, #16 8000e18: e000 b.n 8000e1c 8000e1a: 2301 movs r3, #1 8000e1c: 4a42 ldr r2, [pc, #264] @ (8000f28 ) 8000e1e: 6053 str r3, [r2, #4] 8000e20: e057 b.n 8000ed2 8000e22: 687b ldr r3, [r7, #4] 8000e24: 681b ldr r3, [r3, #0] 8000e26: 4a36 ldr r2, [pc, #216] @ (8000f00 ) 8000e28: 4293 cmp r3, r2 8000e2a: d04f beq.n 8000ecc 8000e2c: 687b ldr r3, [r7, #4] 8000e2e: 681b ldr r3, [r3, #0] 8000e30: 4a34 ldr r2, [pc, #208] @ (8000f04 ) 8000e32: 4293 cmp r3, r2 8000e34: d048 beq.n 8000ec8 8000e36: 687b ldr r3, [r7, #4] 8000e38: 681b ldr r3, [r3, #0] 8000e3a: 4a33 ldr r2, [pc, #204] @ (8000f08 ) 8000e3c: 4293 cmp r3, r2 8000e3e: d040 beq.n 8000ec2 8000e40: 687b ldr r3, [r7, #4] 8000e42: 681b ldr r3, [r3, #0] 8000e44: 4a31 ldr r2, [pc, #196] @ (8000f0c ) 8000e46: 4293 cmp r3, r2 8000e48: d038 beq.n 8000ebc 8000e4a: 687b ldr r3, [r7, #4] 8000e4c: 681b ldr r3, [r3, #0] 8000e4e: 4a30 ldr r2, [pc, #192] @ (8000f10 ) 8000e50: 4293 cmp r3, r2 8000e52: d030 beq.n 8000eb6 8000e54: 687b ldr r3, [r7, #4] 8000e56: 681b ldr r3, [r3, #0] 8000e58: 4a2e ldr r2, [pc, #184] @ (8000f14 ) 8000e5a: 4293 cmp r3, r2 8000e5c: d028 beq.n 8000eb0 8000e5e: 687b ldr r3, [r7, #4] 8000e60: 681b ldr r3, [r3, #0] 8000e62: 4a26 ldr r2, [pc, #152] @ (8000efc ) 8000e64: 4293 cmp r3, r2 8000e66: d020 beq.n 8000eaa 8000e68: 687b ldr r3, [r7, #4] 8000e6a: 681b ldr r3, [r3, #0] 8000e6c: 4a2a ldr r2, [pc, #168] @ (8000f18 ) 8000e6e: 4293 cmp r3, r2 8000e70: d019 beq.n 8000ea6 8000e72: 687b ldr r3, [r7, #4] 8000e74: 681b ldr r3, [r3, #0] 8000e76: 4a29 ldr r2, [pc, #164] @ (8000f1c ) 8000e78: 4293 cmp r3, r2 8000e7a: d012 beq.n 8000ea2 8000e7c: 687b ldr r3, [r7, #4] 8000e7e: 681b ldr r3, [r3, #0] 8000e80: 4a27 ldr r2, [pc, #156] @ (8000f20 ) 8000e82: 4293 cmp r3, r2 8000e84: d00a beq.n 8000e9c 8000e86: 687b ldr r3, [r7, #4] 8000e88: 681b ldr r3, [r3, #0] 8000e8a: 4a26 ldr r2, [pc, #152] @ (8000f24 ) 8000e8c: 4293 cmp r3, r2 8000e8e: d102 bne.n 8000e96 8000e90: f44f 5380 mov.w r3, #4096 @ 0x1000 8000e94: e01b b.n 8000ece 8000e96: f44f 3380 mov.w r3, #65536 @ 0x10000 8000e9a: e018 b.n 8000ece 8000e9c: f44f 7380 mov.w r3, #256 @ 0x100 8000ea0: e015 b.n 8000ece 8000ea2: 2310 movs r3, #16 8000ea4: e013 b.n 8000ece 8000ea6: 2301 movs r3, #1 8000ea8: e011 b.n 8000ece 8000eaa: f04f 7380 mov.w r3, #16777216 @ 0x1000000 8000eae: e00e b.n 8000ece 8000eb0: f44f 1380 mov.w r3, #1048576 @ 0x100000 8000eb4: e00b b.n 8000ece 8000eb6: f44f 3380 mov.w r3, #65536 @ 0x10000 8000eba: e008 b.n 8000ece 8000ebc: f44f 5380 mov.w r3, #4096 @ 0x1000 8000ec0: e005 b.n 8000ece 8000ec2: f44f 7380 mov.w r3, #256 @ 0x100 8000ec6: e002 b.n 8000ece 8000ec8: 2310 movs r3, #16 8000eca: e000 b.n 8000ece 8000ecc: 2301 movs r3, #1 8000ece: 4a17 ldr r2, [pc, #92] @ (8000f2c ) 8000ed0: 6053 str r3, [r2, #4] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8000ed2: 687b ldr r3, [r7, #4] 8000ed4: 2201 movs r2, #1 8000ed6: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8000eda: 687b ldr r3, [r7, #4] 8000edc: 2200 movs r2, #0 8000ede: f883 2020 strb.w r2, [r3, #32] /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) 8000ee2: 687b ldr r3, [r7, #4] 8000ee4: 6b5b ldr r3, [r3, #52] @ 0x34 8000ee6: 2b00 cmp r3, #0 8000ee8: d003 beq.n 8000ef2 { hdma->XferAbortCallback(hdma); 8000eea: 687b ldr r3, [r7, #4] 8000eec: 6b5b ldr r3, [r3, #52] @ 0x34 8000eee: 6878 ldr r0, [r7, #4] 8000ef0: 4798 blx r3 } } return status; 8000ef2: 7bfb ldrb r3, [r7, #15] } 8000ef4: 4618 mov r0, r3 8000ef6: 3710 adds r7, #16 8000ef8: 46bd mov sp, r7 8000efa: bd80 pop {r7, pc} 8000efc: 40020080 .word 0x40020080 8000f00: 40020008 .word 0x40020008 8000f04: 4002001c .word 0x4002001c 8000f08: 40020030 .word 0x40020030 8000f0c: 40020044 .word 0x40020044 8000f10: 40020058 .word 0x40020058 8000f14: 4002006c .word 0x4002006c 8000f18: 40020408 .word 0x40020408 8000f1c: 4002041c .word 0x4002041c 8000f20: 40020430 .word 0x40020430 8000f24: 40020444 .word 0x40020444 8000f28: 40020400 .word 0x40020400 8000f2c: 40020000 .word 0x40020000 08000f30 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8000f30: b480 push {r7} 8000f32: b08b sub sp, #44 @ 0x2c 8000f34: af00 add r7, sp, #0 8000f36: 6078 str r0, [r7, #4] 8000f38: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 8000f3a: 2300 movs r3, #0 8000f3c: 627b str r3, [r7, #36] @ 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 8000f3e: 2300 movs r3, #0 8000f40: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 8000f42: e179 b.n 8001238 { /* Get the IO position */ ioposition = (0x01uL << position); 8000f44: 2201 movs r2, #1 8000f46: 6a7b ldr r3, [r7, #36] @ 0x24 8000f48: fa02 f303 lsl.w r3, r2, r3 8000f4c: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 8000f4e: 683b ldr r3, [r7, #0] 8000f50: 681b ldr r3, [r3, #0] 8000f52: 69fa ldr r2, [r7, #28] 8000f54: 4013 ands r3, r2 8000f56: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 8000f58: 69ba ldr r2, [r7, #24] 8000f5a: 69fb ldr r3, [r7, #28] 8000f5c: 429a cmp r2, r3 8000f5e: f040 8168 bne.w 8001232 { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 8000f62: 683b ldr r3, [r7, #0] 8000f64: 685b ldr r3, [r3, #4] 8000f66: 4a96 ldr r2, [pc, #600] @ (80011c0 ) 8000f68: 4293 cmp r3, r2 8000f6a: d05e beq.n 800102a 8000f6c: 4a94 ldr r2, [pc, #592] @ (80011c0 ) 8000f6e: 4293 cmp r3, r2 8000f70: d875 bhi.n 800105e 8000f72: 4a94 ldr r2, [pc, #592] @ (80011c4 ) 8000f74: 4293 cmp r3, r2 8000f76: d058 beq.n 800102a 8000f78: 4a92 ldr r2, [pc, #584] @ (80011c4 ) 8000f7a: 4293 cmp r3, r2 8000f7c: d86f bhi.n 800105e 8000f7e: 4a92 ldr r2, [pc, #584] @ (80011c8 ) 8000f80: 4293 cmp r3, r2 8000f82: d052 beq.n 800102a 8000f84: 4a90 ldr r2, [pc, #576] @ (80011c8 ) 8000f86: 4293 cmp r3, r2 8000f88: d869 bhi.n 800105e 8000f8a: 4a90 ldr r2, [pc, #576] @ (80011cc ) 8000f8c: 4293 cmp r3, r2 8000f8e: d04c beq.n 800102a 8000f90: 4a8e ldr r2, [pc, #568] @ (80011cc ) 8000f92: 4293 cmp r3, r2 8000f94: d863 bhi.n 800105e 8000f96: 4a8e ldr r2, [pc, #568] @ (80011d0 ) 8000f98: 4293 cmp r3, r2 8000f9a: d046 beq.n 800102a 8000f9c: 4a8c ldr r2, [pc, #560] @ (80011d0 ) 8000f9e: 4293 cmp r3, r2 8000fa0: d85d bhi.n 800105e 8000fa2: 2b12 cmp r3, #18 8000fa4: d82a bhi.n 8000ffc 8000fa6: 2b12 cmp r3, #18 8000fa8: d859 bhi.n 800105e 8000faa: a201 add r2, pc, #4 @ (adr r2, 8000fb0 ) 8000fac: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8000fb0: 0800102b .word 0x0800102b 8000fb4: 08001005 .word 0x08001005 8000fb8: 08001017 .word 0x08001017 8000fbc: 08001059 .word 0x08001059 8000fc0: 0800105f .word 0x0800105f 8000fc4: 0800105f .word 0x0800105f 8000fc8: 0800105f .word 0x0800105f 8000fcc: 0800105f .word 0x0800105f 8000fd0: 0800105f .word 0x0800105f 8000fd4: 0800105f .word 0x0800105f 8000fd8: 0800105f .word 0x0800105f 8000fdc: 0800105f .word 0x0800105f 8000fe0: 0800105f .word 0x0800105f 8000fe4: 0800105f .word 0x0800105f 8000fe8: 0800105f .word 0x0800105f 8000fec: 0800105f .word 0x0800105f 8000ff0: 0800105f .word 0x0800105f 8000ff4: 0800100d .word 0x0800100d 8000ff8: 08001021 .word 0x08001021 8000ffc: 4a75 ldr r2, [pc, #468] @ (80011d4 ) 8000ffe: 4293 cmp r3, r2 8001000: d013 beq.n 800102a config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 8001002: e02c b.n 800105e config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 8001004: 683b ldr r3, [r7, #0] 8001006: 68db ldr r3, [r3, #12] 8001008: 623b str r3, [r7, #32] break; 800100a: e029 b.n 8001060 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 800100c: 683b ldr r3, [r7, #0] 800100e: 68db ldr r3, [r3, #12] 8001010: 3304 adds r3, #4 8001012: 623b str r3, [r7, #32] break; 8001014: e024 b.n 8001060 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 8001016: 683b ldr r3, [r7, #0] 8001018: 68db ldr r3, [r3, #12] 800101a: 3308 adds r3, #8 800101c: 623b str r3, [r7, #32] break; 800101e: e01f b.n 8001060 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 8001020: 683b ldr r3, [r7, #0] 8001022: 68db ldr r3, [r3, #12] 8001024: 330c adds r3, #12 8001026: 623b str r3, [r7, #32] break; 8001028: e01a b.n 8001060 if (GPIO_Init->Pull == GPIO_NOPULL) 800102a: 683b ldr r3, [r7, #0] 800102c: 689b ldr r3, [r3, #8] 800102e: 2b00 cmp r3, #0 8001030: d102 bne.n 8001038 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 8001032: 2304 movs r3, #4 8001034: 623b str r3, [r7, #32] break; 8001036: e013 b.n 8001060 else if (GPIO_Init->Pull == GPIO_PULLUP) 8001038: 683b ldr r3, [r7, #0] 800103a: 689b ldr r3, [r3, #8] 800103c: 2b01 cmp r3, #1 800103e: d105 bne.n 800104c config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8001040: 2308 movs r3, #8 8001042: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 8001044: 687b ldr r3, [r7, #4] 8001046: 69fa ldr r2, [r7, #28] 8001048: 611a str r2, [r3, #16] break; 800104a: e009 b.n 8001060 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 800104c: 2308 movs r3, #8 800104e: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 8001050: 687b ldr r3, [r7, #4] 8001052: 69fa ldr r2, [r7, #28] 8001054: 615a str r2, [r3, #20] break; 8001056: e003 b.n 8001060 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 8001058: 2300 movs r3, #0 800105a: 623b str r3, [r7, #32] break; 800105c: e000 b.n 8001060 break; 800105e: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 8001060: 69bb ldr r3, [r7, #24] 8001062: 2bff cmp r3, #255 @ 0xff 8001064: d801 bhi.n 800106a 8001066: 687b ldr r3, [r7, #4] 8001068: e001 b.n 800106e 800106a: 687b ldr r3, [r7, #4] 800106c: 3304 adds r3, #4 800106e: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 8001070: 69bb ldr r3, [r7, #24] 8001072: 2bff cmp r3, #255 @ 0xff 8001074: d802 bhi.n 800107c 8001076: 6a7b ldr r3, [r7, #36] @ 0x24 8001078: 009b lsls r3, r3, #2 800107a: e002 b.n 8001082 800107c: 6a7b ldr r3, [r7, #36] @ 0x24 800107e: 3b08 subs r3, #8 8001080: 009b lsls r3, r3, #2 8001082: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 8001084: 697b ldr r3, [r7, #20] 8001086: 681a ldr r2, [r3, #0] 8001088: 210f movs r1, #15 800108a: 693b ldr r3, [r7, #16] 800108c: fa01 f303 lsl.w r3, r1, r3 8001090: 43db mvns r3, r3 8001092: 401a ands r2, r3 8001094: 6a39 ldr r1, [r7, #32] 8001096: 693b ldr r3, [r7, #16] 8001098: fa01 f303 lsl.w r3, r1, r3 800109c: 431a orrs r2, r3 800109e: 697b ldr r3, [r7, #20] 80010a0: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 80010a2: 683b ldr r3, [r7, #0] 80010a4: 685b ldr r3, [r3, #4] 80010a6: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80010aa: 2b00 cmp r3, #0 80010ac: f000 80c1 beq.w 8001232 { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 80010b0: 4b49 ldr r3, [pc, #292] @ (80011d8 ) 80010b2: 699b ldr r3, [r3, #24] 80010b4: 4a48 ldr r2, [pc, #288] @ (80011d8 ) 80010b6: f043 0301 orr.w r3, r3, #1 80010ba: 6193 str r3, [r2, #24] 80010bc: 4b46 ldr r3, [pc, #280] @ (80011d8 ) 80010be: 699b ldr r3, [r3, #24] 80010c0: f003 0301 and.w r3, r3, #1 80010c4: 60bb str r3, [r7, #8] 80010c6: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 80010c8: 4a44 ldr r2, [pc, #272] @ (80011dc ) 80010ca: 6a7b ldr r3, [r7, #36] @ 0x24 80010cc: 089b lsrs r3, r3, #2 80010ce: 3302 adds r3, #2 80010d0: f852 3023 ldr.w r3, [r2, r3, lsl #2] 80010d4: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 80010d6: 6a7b ldr r3, [r7, #36] @ 0x24 80010d8: f003 0303 and.w r3, r3, #3 80010dc: 009b lsls r3, r3, #2 80010de: 220f movs r2, #15 80010e0: fa02 f303 lsl.w r3, r2, r3 80010e4: 43db mvns r3, r3 80010e6: 68fa ldr r2, [r7, #12] 80010e8: 4013 ands r3, r2 80010ea: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 80010ec: 687b ldr r3, [r7, #4] 80010ee: 4a3c ldr r2, [pc, #240] @ (80011e0 ) 80010f0: 4293 cmp r3, r2 80010f2: d01f beq.n 8001134 80010f4: 687b ldr r3, [r7, #4] 80010f6: 4a3b ldr r2, [pc, #236] @ (80011e4 ) 80010f8: 4293 cmp r3, r2 80010fa: d019 beq.n 8001130 80010fc: 687b ldr r3, [r7, #4] 80010fe: 4a3a ldr r2, [pc, #232] @ (80011e8 ) 8001100: 4293 cmp r3, r2 8001102: d013 beq.n 800112c 8001104: 687b ldr r3, [r7, #4] 8001106: 4a39 ldr r2, [pc, #228] @ (80011ec ) 8001108: 4293 cmp r3, r2 800110a: d00d beq.n 8001128 800110c: 687b ldr r3, [r7, #4] 800110e: 4a38 ldr r2, [pc, #224] @ (80011f0 ) 8001110: 4293 cmp r3, r2 8001112: d007 beq.n 8001124 8001114: 687b ldr r3, [r7, #4] 8001116: 4a37 ldr r2, [pc, #220] @ (80011f4 ) 8001118: 4293 cmp r3, r2 800111a: d101 bne.n 8001120 800111c: 2305 movs r3, #5 800111e: e00a b.n 8001136 8001120: 2306 movs r3, #6 8001122: e008 b.n 8001136 8001124: 2304 movs r3, #4 8001126: e006 b.n 8001136 8001128: 2303 movs r3, #3 800112a: e004 b.n 8001136 800112c: 2302 movs r3, #2 800112e: e002 b.n 8001136 8001130: 2301 movs r3, #1 8001132: e000 b.n 8001136 8001134: 2300 movs r3, #0 8001136: 6a7a ldr r2, [r7, #36] @ 0x24 8001138: f002 0203 and.w r2, r2, #3 800113c: 0092 lsls r2, r2, #2 800113e: 4093 lsls r3, r2 8001140: 68fa ldr r2, [r7, #12] 8001142: 4313 orrs r3, r2 8001144: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 8001146: 4925 ldr r1, [pc, #148] @ (80011dc ) 8001148: 6a7b ldr r3, [r7, #36] @ 0x24 800114a: 089b lsrs r3, r3, #2 800114c: 3302 adds r3, #2 800114e: 68fa ldr r2, [r7, #12] 8001150: f841 2023 str.w r2, [r1, r3, lsl #2] /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 8001154: 683b ldr r3, [r7, #0] 8001156: 685b ldr r3, [r3, #4] 8001158: f403 1380 and.w r3, r3, #1048576 @ 0x100000 800115c: 2b00 cmp r3, #0 800115e: d006 beq.n 800116e { SET_BIT(EXTI->RTSR, iocurrent); 8001160: 4b25 ldr r3, [pc, #148] @ (80011f8 ) 8001162: 689a ldr r2, [r3, #8] 8001164: 4924 ldr r1, [pc, #144] @ (80011f8 ) 8001166: 69bb ldr r3, [r7, #24] 8001168: 4313 orrs r3, r2 800116a: 608b str r3, [r1, #8] 800116c: e006 b.n 800117c } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 800116e: 4b22 ldr r3, [pc, #136] @ (80011f8 ) 8001170: 689a ldr r2, [r3, #8] 8001172: 69bb ldr r3, [r7, #24] 8001174: 43db mvns r3, r3 8001176: 4920 ldr r1, [pc, #128] @ (80011f8 ) 8001178: 4013 ands r3, r2 800117a: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 800117c: 683b ldr r3, [r7, #0] 800117e: 685b ldr r3, [r3, #4] 8001180: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8001184: 2b00 cmp r3, #0 8001186: d006 beq.n 8001196 { SET_BIT(EXTI->FTSR, iocurrent); 8001188: 4b1b ldr r3, [pc, #108] @ (80011f8 ) 800118a: 68da ldr r2, [r3, #12] 800118c: 491a ldr r1, [pc, #104] @ (80011f8 ) 800118e: 69bb ldr r3, [r7, #24] 8001190: 4313 orrs r3, r2 8001192: 60cb str r3, [r1, #12] 8001194: e006 b.n 80011a4 } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 8001196: 4b18 ldr r3, [pc, #96] @ (80011f8 ) 8001198: 68da ldr r2, [r3, #12] 800119a: 69bb ldr r3, [r7, #24] 800119c: 43db mvns r3, r3 800119e: 4916 ldr r1, [pc, #88] @ (80011f8 ) 80011a0: 4013 ands r3, r2 80011a2: 60cb str r3, [r1, #12] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 80011a4: 683b ldr r3, [r7, #0] 80011a6: 685b ldr r3, [r3, #4] 80011a8: f403 3300 and.w r3, r3, #131072 @ 0x20000 80011ac: 2b00 cmp r3, #0 80011ae: d025 beq.n 80011fc { SET_BIT(EXTI->EMR, iocurrent); 80011b0: 4b11 ldr r3, [pc, #68] @ (80011f8 ) 80011b2: 685a ldr r2, [r3, #4] 80011b4: 4910 ldr r1, [pc, #64] @ (80011f8 ) 80011b6: 69bb ldr r3, [r7, #24] 80011b8: 4313 orrs r3, r2 80011ba: 604b str r3, [r1, #4] 80011bc: e025 b.n 800120a 80011be: bf00 nop 80011c0: 10320000 .word 0x10320000 80011c4: 10310000 .word 0x10310000 80011c8: 10220000 .word 0x10220000 80011cc: 10210000 .word 0x10210000 80011d0: 10120000 .word 0x10120000 80011d4: 10110000 .word 0x10110000 80011d8: 40021000 .word 0x40021000 80011dc: 40010000 .word 0x40010000 80011e0: 40010800 .word 0x40010800 80011e4: 40010c00 .word 0x40010c00 80011e8: 40011000 .word 0x40011000 80011ec: 40011400 .word 0x40011400 80011f0: 40011800 .word 0x40011800 80011f4: 40011c00 .word 0x40011c00 80011f8: 40010400 .word 0x40010400 } else { CLEAR_BIT(EXTI->EMR, iocurrent); 80011fc: 4b15 ldr r3, [pc, #84] @ (8001254 ) 80011fe: 685a ldr r2, [r3, #4] 8001200: 69bb ldr r3, [r7, #24] 8001202: 43db mvns r3, r3 8001204: 4913 ldr r1, [pc, #76] @ (8001254 ) 8001206: 4013 ands r3, r2 8001208: 604b str r3, [r1, #4] } /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 800120a: 683b ldr r3, [r7, #0] 800120c: 685b ldr r3, [r3, #4] 800120e: f403 3380 and.w r3, r3, #65536 @ 0x10000 8001212: 2b00 cmp r3, #0 8001214: d006 beq.n 8001224 { SET_BIT(EXTI->IMR, iocurrent); 8001216: 4b0f ldr r3, [pc, #60] @ (8001254 ) 8001218: 681a ldr r2, [r3, #0] 800121a: 490e ldr r1, [pc, #56] @ (8001254 ) 800121c: 69bb ldr r3, [r7, #24] 800121e: 4313 orrs r3, r2 8001220: 600b str r3, [r1, #0] 8001222: e006 b.n 8001232 } else { CLEAR_BIT(EXTI->IMR, iocurrent); 8001224: 4b0b ldr r3, [pc, #44] @ (8001254 ) 8001226: 681a ldr r2, [r3, #0] 8001228: 69bb ldr r3, [r7, #24] 800122a: 43db mvns r3, r3 800122c: 4909 ldr r1, [pc, #36] @ (8001254 ) 800122e: 4013 ands r3, r2 8001230: 600b str r3, [r1, #0] } } } position++; 8001232: 6a7b ldr r3, [r7, #36] @ 0x24 8001234: 3301 adds r3, #1 8001236: 627b str r3, [r7, #36] @ 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 8001238: 683b ldr r3, [r7, #0] 800123a: 681a ldr r2, [r3, #0] 800123c: 6a7b ldr r3, [r7, #36] @ 0x24 800123e: fa22 f303 lsr.w r3, r2, r3 8001242: 2b00 cmp r3, #0 8001244: f47f ae7e bne.w 8000f44 } } 8001248: bf00 nop 800124a: bf00 nop 800124c: 372c adds r7, #44 @ 0x2c 800124e: 46bd mov sp, r7 8001250: bc80 pop {r7} 8001252: 4770 bx lr 8001254: 40010400 .word 0x40010400 08001258 : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 8001258: b480 push {r7} 800125a: b085 sub sp, #20 800125c: af00 add r7, sp, #0 800125e: 6078 str r0, [r7, #4] 8001260: 460b mov r3, r1 8001262: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 8001264: 687b ldr r3, [r7, #4] 8001266: 689a ldr r2, [r3, #8] 8001268: 887b ldrh r3, [r7, #2] 800126a: 4013 ands r3, r2 800126c: 2b00 cmp r3, #0 800126e: d002 beq.n 8001276 { bitstatus = GPIO_PIN_SET; 8001270: 2301 movs r3, #1 8001272: 73fb strb r3, [r7, #15] 8001274: e001 b.n 800127a } else { bitstatus = GPIO_PIN_RESET; 8001276: 2300 movs r3, #0 8001278: 73fb strb r3, [r7, #15] } return bitstatus; 800127a: 7bfb ldrb r3, [r7, #15] } 800127c: 4618 mov r0, r3 800127e: 3714 adds r7, #20 8001280: 46bd mov sp, r7 8001282: bc80 pop {r7} 8001284: 4770 bx lr 08001286 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8001286: b480 push {r7} 8001288: b083 sub sp, #12 800128a: af00 add r7, sp, #0 800128c: 6078 str r0, [r7, #4] 800128e: 460b mov r3, r1 8001290: 807b strh r3, [r7, #2] 8001292: 4613 mov r3, r2 8001294: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8001296: 787b ldrb r3, [r7, #1] 8001298: 2b00 cmp r3, #0 800129a: d003 beq.n 80012a4 { GPIOx->BSRR = GPIO_Pin; 800129c: 887a ldrh r2, [r7, #2] 800129e: 687b ldr r3, [r7, #4] 80012a0: 611a str r2, [r3, #16] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; } } 80012a2: e003 b.n 80012ac GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; 80012a4: 887b ldrh r3, [r7, #2] 80012a6: 041a lsls r2, r3, #16 80012a8: 687b ldr r3, [r7, #4] 80012aa: 611a str r2, [r3, #16] } 80012ac: bf00 nop 80012ae: 370c adds r7, #12 80012b0: 46bd mov sp, r7 80012b2: bc80 pop {r7} 80012b4: 4770 bx lr 080012b6 : * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral * @param GPIO_Pin: Specifies the pins to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 80012b6: b480 push {r7} 80012b8: b085 sub sp, #20 80012ba: af00 add r7, sp, #0 80012bc: 6078 str r0, [r7, #4] 80012be: 460b mov r3, r1 80012c0: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); /* get current Output Data Register value */ odr = GPIOx->ODR; 80012c2: 687b ldr r3, [r7, #4] 80012c4: 68db ldr r3, [r3, #12] 80012c6: 60fb str r3, [r7, #12] /* Set selected pins that were at low level, and reset ones that were high */ GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); 80012c8: 887a ldrh r2, [r7, #2] 80012ca: 68fb ldr r3, [r7, #12] 80012cc: 4013 ands r3, r2 80012ce: 041a lsls r2, r3, #16 80012d0: 68fb ldr r3, [r7, #12] 80012d2: 43d9 mvns r1, r3 80012d4: 887b ldrh r3, [r7, #2] 80012d6: 400b ands r3, r1 80012d8: 431a orrs r2, r3 80012da: 687b ldr r3, [r7, #4] 80012dc: 611a str r2, [r3, #16] } 80012de: bf00 nop 80012e0: 3714 adds r7, #20 80012e2: 46bd mov sp, r7 80012e4: bc80 pop {r7} 80012e6: 4770 bx lr 080012e8 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 80012e8: b580 push {r7, lr} 80012ea: b086 sub sp, #24 80012ec: af00 add r7, sp, #0 80012ee: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 80012f0: 687b ldr r3, [r7, #4] 80012f2: 2b00 cmp r3, #0 80012f4: d101 bne.n 80012fa { return HAL_ERROR; 80012f6: 2301 movs r3, #1 80012f8: e272 b.n 80017e0 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 80012fa: 687b ldr r3, [r7, #4] 80012fc: 681b ldr r3, [r3, #0] 80012fe: f003 0301 and.w r3, r3, #1 8001302: 2b00 cmp r3, #0 8001304: f000 8087 beq.w 8001416 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 8001308: 4b92 ldr r3, [pc, #584] @ (8001554 ) 800130a: 685b ldr r3, [r3, #4] 800130c: f003 030c and.w r3, r3, #12 8001310: 2b04 cmp r3, #4 8001312: d00c beq.n 800132e || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 8001314: 4b8f ldr r3, [pc, #572] @ (8001554 ) 8001316: 685b ldr r3, [r3, #4] 8001318: f003 030c and.w r3, r3, #12 800131c: 2b08 cmp r3, #8 800131e: d112 bne.n 8001346 8001320: 4b8c ldr r3, [pc, #560] @ (8001554 ) 8001322: 685b ldr r3, [r3, #4] 8001324: f403 3380 and.w r3, r3, #65536 @ 0x10000 8001328: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800132c: d10b bne.n 8001346 { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800132e: 4b89 ldr r3, [pc, #548] @ (8001554 ) 8001330: 681b ldr r3, [r3, #0] 8001332: f403 3300 and.w r3, r3, #131072 @ 0x20000 8001336: 2b00 cmp r3, #0 8001338: d06c beq.n 8001414 800133a: 687b ldr r3, [r7, #4] 800133c: 685b ldr r3, [r3, #4] 800133e: 2b00 cmp r3, #0 8001340: d168 bne.n 8001414 { return HAL_ERROR; 8001342: 2301 movs r3, #1 8001344: e24c b.n 80017e0 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8001346: 687b ldr r3, [r7, #4] 8001348: 685b ldr r3, [r3, #4] 800134a: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800134e: d106 bne.n 800135e 8001350: 4b80 ldr r3, [pc, #512] @ (8001554 ) 8001352: 681b ldr r3, [r3, #0] 8001354: 4a7f ldr r2, [pc, #508] @ (8001554 ) 8001356: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800135a: 6013 str r3, [r2, #0] 800135c: e02e b.n 80013bc 800135e: 687b ldr r3, [r7, #4] 8001360: 685b ldr r3, [r3, #4] 8001362: 2b00 cmp r3, #0 8001364: d10c bne.n 8001380 8001366: 4b7b ldr r3, [pc, #492] @ (8001554 ) 8001368: 681b ldr r3, [r3, #0] 800136a: 4a7a ldr r2, [pc, #488] @ (8001554 ) 800136c: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8001370: 6013 str r3, [r2, #0] 8001372: 4b78 ldr r3, [pc, #480] @ (8001554 ) 8001374: 681b ldr r3, [r3, #0] 8001376: 4a77 ldr r2, [pc, #476] @ (8001554 ) 8001378: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800137c: 6013 str r3, [r2, #0] 800137e: e01d b.n 80013bc 8001380: 687b ldr r3, [r7, #4] 8001382: 685b ldr r3, [r3, #4] 8001384: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 8001388: d10c bne.n 80013a4 800138a: 4b72 ldr r3, [pc, #456] @ (8001554 ) 800138c: 681b ldr r3, [r3, #0] 800138e: 4a71 ldr r2, [pc, #452] @ (8001554 ) 8001390: f443 2380 orr.w r3, r3, #262144 @ 0x40000 8001394: 6013 str r3, [r2, #0] 8001396: 4b6f ldr r3, [pc, #444] @ (8001554 ) 8001398: 681b ldr r3, [r3, #0] 800139a: 4a6e ldr r2, [pc, #440] @ (8001554 ) 800139c: f443 3380 orr.w r3, r3, #65536 @ 0x10000 80013a0: 6013 str r3, [r2, #0] 80013a2: e00b b.n 80013bc 80013a4: 4b6b ldr r3, [pc, #428] @ (8001554 ) 80013a6: 681b ldr r3, [r3, #0] 80013a8: 4a6a ldr r2, [pc, #424] @ (8001554 ) 80013aa: f423 3380 bic.w r3, r3, #65536 @ 0x10000 80013ae: 6013 str r3, [r2, #0] 80013b0: 4b68 ldr r3, [pc, #416] @ (8001554 ) 80013b2: 681b ldr r3, [r3, #0] 80013b4: 4a67 ldr r2, [pc, #412] @ (8001554 ) 80013b6: f423 2380 bic.w r3, r3, #262144 @ 0x40000 80013ba: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 80013bc: 687b ldr r3, [r7, #4] 80013be: 685b ldr r3, [r3, #4] 80013c0: 2b00 cmp r3, #0 80013c2: d013 beq.n 80013ec { /* Get Start Tick */ tickstart = HAL_GetTick(); 80013c4: f7ff fb1a bl 80009fc 80013c8: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80013ca: e008 b.n 80013de { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 80013cc: f7ff fb16 bl 80009fc 80013d0: 4602 mov r2, r0 80013d2: 693b ldr r3, [r7, #16] 80013d4: 1ad3 subs r3, r2, r3 80013d6: 2b64 cmp r3, #100 @ 0x64 80013d8: d901 bls.n 80013de { return HAL_TIMEOUT; 80013da: 2303 movs r3, #3 80013dc: e200 b.n 80017e0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80013de: 4b5d ldr r3, [pc, #372] @ (8001554 ) 80013e0: 681b ldr r3, [r3, #0] 80013e2: f403 3300 and.w r3, r3, #131072 @ 0x20000 80013e6: 2b00 cmp r3, #0 80013e8: d0f0 beq.n 80013cc 80013ea: e014 b.n 8001416 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 80013ec: f7ff fb06 bl 80009fc 80013f0: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 80013f2: e008 b.n 8001406 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 80013f4: f7ff fb02 bl 80009fc 80013f8: 4602 mov r2, r0 80013fa: 693b ldr r3, [r7, #16] 80013fc: 1ad3 subs r3, r2, r3 80013fe: 2b64 cmp r3, #100 @ 0x64 8001400: d901 bls.n 8001406 { return HAL_TIMEOUT; 8001402: 2303 movs r3, #3 8001404: e1ec b.n 80017e0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8001406: 4b53 ldr r3, [pc, #332] @ (8001554 ) 8001408: 681b ldr r3, [r3, #0] 800140a: f403 3300 and.w r3, r3, #131072 @ 0x20000 800140e: 2b00 cmp r3, #0 8001410: d1f0 bne.n 80013f4 8001412: e000 b.n 8001416 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8001414: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8001416: 687b ldr r3, [r7, #4] 8001418: 681b ldr r3, [r3, #0] 800141a: f003 0302 and.w r3, r3, #2 800141e: 2b00 cmp r3, #0 8001420: d063 beq.n 80014ea /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 8001422: 4b4c ldr r3, [pc, #304] @ (8001554 ) 8001424: 685b ldr r3, [r3, #4] 8001426: f003 030c and.w r3, r3, #12 800142a: 2b00 cmp r3, #0 800142c: d00b beq.n 8001446 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 800142e: 4b49 ldr r3, [pc, #292] @ (8001554 ) 8001430: 685b ldr r3, [r3, #4] 8001432: f003 030c and.w r3, r3, #12 8001436: 2b08 cmp r3, #8 8001438: d11c bne.n 8001474 800143a: 4b46 ldr r3, [pc, #280] @ (8001554 ) 800143c: 685b ldr r3, [r3, #4] 800143e: f403 3380 and.w r3, r3, #65536 @ 0x10000 8001442: 2b00 cmp r3, #0 8001444: d116 bne.n 8001474 { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8001446: 4b43 ldr r3, [pc, #268] @ (8001554 ) 8001448: 681b ldr r3, [r3, #0] 800144a: f003 0302 and.w r3, r3, #2 800144e: 2b00 cmp r3, #0 8001450: d005 beq.n 800145e 8001452: 687b ldr r3, [r7, #4] 8001454: 691b ldr r3, [r3, #16] 8001456: 2b01 cmp r3, #1 8001458: d001 beq.n 800145e { return HAL_ERROR; 800145a: 2301 movs r3, #1 800145c: e1c0 b.n 80017e0 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800145e: 4b3d ldr r3, [pc, #244] @ (8001554 ) 8001460: 681b ldr r3, [r3, #0] 8001462: f023 02f8 bic.w r2, r3, #248 @ 0xf8 8001466: 687b ldr r3, [r7, #4] 8001468: 695b ldr r3, [r3, #20] 800146a: 00db lsls r3, r3, #3 800146c: 4939 ldr r1, [pc, #228] @ (8001554 ) 800146e: 4313 orrs r3, r2 8001470: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8001472: e03a b.n 80014ea } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8001474: 687b ldr r3, [r7, #4] 8001476: 691b ldr r3, [r3, #16] 8001478: 2b00 cmp r3, #0 800147a: d020 beq.n 80014be { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 800147c: 4b36 ldr r3, [pc, #216] @ (8001558 ) 800147e: 2201 movs r2, #1 8001480: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001482: f7ff fabb bl 80009fc 8001486: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8001488: e008 b.n 800149c { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800148a: f7ff fab7 bl 80009fc 800148e: 4602 mov r2, r0 8001490: 693b ldr r3, [r7, #16] 8001492: 1ad3 subs r3, r2, r3 8001494: 2b02 cmp r3, #2 8001496: d901 bls.n 800149c { return HAL_TIMEOUT; 8001498: 2303 movs r3, #3 800149a: e1a1 b.n 80017e0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 800149c: 4b2d ldr r3, [pc, #180] @ (8001554 ) 800149e: 681b ldr r3, [r3, #0] 80014a0: f003 0302 and.w r3, r3, #2 80014a4: 2b00 cmp r3, #0 80014a6: d0f0 beq.n 800148a } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80014a8: 4b2a ldr r3, [pc, #168] @ (8001554 ) 80014aa: 681b ldr r3, [r3, #0] 80014ac: f023 02f8 bic.w r2, r3, #248 @ 0xf8 80014b0: 687b ldr r3, [r7, #4] 80014b2: 695b ldr r3, [r3, #20] 80014b4: 00db lsls r3, r3, #3 80014b6: 4927 ldr r1, [pc, #156] @ (8001554 ) 80014b8: 4313 orrs r3, r2 80014ba: 600b str r3, [r1, #0] 80014bc: e015 b.n 80014ea } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 80014be: 4b26 ldr r3, [pc, #152] @ (8001558 ) 80014c0: 2200 movs r2, #0 80014c2: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80014c4: f7ff fa9a bl 80009fc 80014c8: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 80014ca: e008 b.n 80014de { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 80014cc: f7ff fa96 bl 80009fc 80014d0: 4602 mov r2, r0 80014d2: 693b ldr r3, [r7, #16] 80014d4: 1ad3 subs r3, r2, r3 80014d6: 2b02 cmp r3, #2 80014d8: d901 bls.n 80014de { return HAL_TIMEOUT; 80014da: 2303 movs r3, #3 80014dc: e180 b.n 80017e0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 80014de: 4b1d ldr r3, [pc, #116] @ (8001554 ) 80014e0: 681b ldr r3, [r3, #0] 80014e2: f003 0302 and.w r3, r3, #2 80014e6: 2b00 cmp r3, #0 80014e8: d1f0 bne.n 80014cc } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 80014ea: 687b ldr r3, [r7, #4] 80014ec: 681b ldr r3, [r3, #0] 80014ee: f003 0308 and.w r3, r3, #8 80014f2: 2b00 cmp r3, #0 80014f4: d03a beq.n 800156c { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 80014f6: 687b ldr r3, [r7, #4] 80014f8: 699b ldr r3, [r3, #24] 80014fa: 2b00 cmp r3, #0 80014fc: d019 beq.n 8001532 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 80014fe: 4b17 ldr r3, [pc, #92] @ (800155c ) 8001500: 2201 movs r2, #1 8001502: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001504: f7ff fa7a bl 80009fc 8001508: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 800150a: e008 b.n 800151e { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800150c: f7ff fa76 bl 80009fc 8001510: 4602 mov r2, r0 8001512: 693b ldr r3, [r7, #16] 8001514: 1ad3 subs r3, r2, r3 8001516: 2b02 cmp r3, #2 8001518: d901 bls.n 800151e { return HAL_TIMEOUT; 800151a: 2303 movs r3, #3 800151c: e160 b.n 80017e0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 800151e: 4b0d ldr r3, [pc, #52] @ (8001554 ) 8001520: 6a5b ldr r3, [r3, #36] @ 0x24 8001522: f003 0302 and.w r3, r3, #2 8001526: 2b00 cmp r3, #0 8001528: d0f0 beq.n 800150c } } /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ RCC_Delay(1); 800152a: 2001 movs r0, #1 800152c: f000 fad0 bl 8001ad0 8001530: e01c b.n 800156c } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8001532: 4b0a ldr r3, [pc, #40] @ (800155c ) 8001534: 2200 movs r2, #0 8001536: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001538: f7ff fa60 bl 80009fc 800153c: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 800153e: e00f b.n 8001560 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8001540: f7ff fa5c bl 80009fc 8001544: 4602 mov r2, r0 8001546: 693b ldr r3, [r7, #16] 8001548: 1ad3 subs r3, r2, r3 800154a: 2b02 cmp r3, #2 800154c: d908 bls.n 8001560 { return HAL_TIMEOUT; 800154e: 2303 movs r3, #3 8001550: e146 b.n 80017e0 8001552: bf00 nop 8001554: 40021000 .word 0x40021000 8001558: 42420000 .word 0x42420000 800155c: 42420480 .word 0x42420480 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8001560: 4b92 ldr r3, [pc, #584] @ (80017ac ) 8001562: 6a5b ldr r3, [r3, #36] @ 0x24 8001564: f003 0302 and.w r3, r3, #2 8001568: 2b00 cmp r3, #0 800156a: d1e9 bne.n 8001540 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 800156c: 687b ldr r3, [r7, #4] 800156e: 681b ldr r3, [r3, #0] 8001570: f003 0304 and.w r3, r3, #4 8001574: 2b00 cmp r3, #0 8001576: f000 80a6 beq.w 80016c6 { FlagStatus pwrclkchanged = RESET; 800157a: 2300 movs r3, #0 800157c: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 800157e: 4b8b ldr r3, [pc, #556] @ (80017ac ) 8001580: 69db ldr r3, [r3, #28] 8001582: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8001586: 2b00 cmp r3, #0 8001588: d10d bne.n 80015a6 { __HAL_RCC_PWR_CLK_ENABLE(); 800158a: 4b88 ldr r3, [pc, #544] @ (80017ac ) 800158c: 69db ldr r3, [r3, #28] 800158e: 4a87 ldr r2, [pc, #540] @ (80017ac ) 8001590: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8001594: 61d3 str r3, [r2, #28] 8001596: 4b85 ldr r3, [pc, #532] @ (80017ac ) 8001598: 69db ldr r3, [r3, #28] 800159a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800159e: 60bb str r3, [r7, #8] 80015a0: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 80015a2: 2301 movs r3, #1 80015a4: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80015a6: 4b82 ldr r3, [pc, #520] @ (80017b0 ) 80015a8: 681b ldr r3, [r3, #0] 80015aa: f403 7380 and.w r3, r3, #256 @ 0x100 80015ae: 2b00 cmp r3, #0 80015b0: d118 bne.n 80015e4 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 80015b2: 4b7f ldr r3, [pc, #508] @ (80017b0 ) 80015b4: 681b ldr r3, [r3, #0] 80015b6: 4a7e ldr r2, [pc, #504] @ (80017b0 ) 80015b8: f443 7380 orr.w r3, r3, #256 @ 0x100 80015bc: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 80015be: f7ff fa1d bl 80009fc 80015c2: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80015c4: e008 b.n 80015d8 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 80015c6: f7ff fa19 bl 80009fc 80015ca: 4602 mov r2, r0 80015cc: 693b ldr r3, [r7, #16] 80015ce: 1ad3 subs r3, r2, r3 80015d0: 2b64 cmp r3, #100 @ 0x64 80015d2: d901 bls.n 80015d8 { return HAL_TIMEOUT; 80015d4: 2303 movs r3, #3 80015d6: e103 b.n 80017e0 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80015d8: 4b75 ldr r3, [pc, #468] @ (80017b0 ) 80015da: 681b ldr r3, [r3, #0] 80015dc: f403 7380 and.w r3, r3, #256 @ 0x100 80015e0: 2b00 cmp r3, #0 80015e2: d0f0 beq.n 80015c6 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 80015e4: 687b ldr r3, [r7, #4] 80015e6: 68db ldr r3, [r3, #12] 80015e8: 2b01 cmp r3, #1 80015ea: d106 bne.n 80015fa 80015ec: 4b6f ldr r3, [pc, #444] @ (80017ac ) 80015ee: 6a1b ldr r3, [r3, #32] 80015f0: 4a6e ldr r2, [pc, #440] @ (80017ac ) 80015f2: f043 0301 orr.w r3, r3, #1 80015f6: 6213 str r3, [r2, #32] 80015f8: e02d b.n 8001656 80015fa: 687b ldr r3, [r7, #4] 80015fc: 68db ldr r3, [r3, #12] 80015fe: 2b00 cmp r3, #0 8001600: d10c bne.n 800161c 8001602: 4b6a ldr r3, [pc, #424] @ (80017ac ) 8001604: 6a1b ldr r3, [r3, #32] 8001606: 4a69 ldr r2, [pc, #420] @ (80017ac ) 8001608: f023 0301 bic.w r3, r3, #1 800160c: 6213 str r3, [r2, #32] 800160e: 4b67 ldr r3, [pc, #412] @ (80017ac ) 8001610: 6a1b ldr r3, [r3, #32] 8001612: 4a66 ldr r2, [pc, #408] @ (80017ac ) 8001614: f023 0304 bic.w r3, r3, #4 8001618: 6213 str r3, [r2, #32] 800161a: e01c b.n 8001656 800161c: 687b ldr r3, [r7, #4] 800161e: 68db ldr r3, [r3, #12] 8001620: 2b05 cmp r3, #5 8001622: d10c bne.n 800163e 8001624: 4b61 ldr r3, [pc, #388] @ (80017ac ) 8001626: 6a1b ldr r3, [r3, #32] 8001628: 4a60 ldr r2, [pc, #384] @ (80017ac ) 800162a: f043 0304 orr.w r3, r3, #4 800162e: 6213 str r3, [r2, #32] 8001630: 4b5e ldr r3, [pc, #376] @ (80017ac ) 8001632: 6a1b ldr r3, [r3, #32] 8001634: 4a5d ldr r2, [pc, #372] @ (80017ac ) 8001636: f043 0301 orr.w r3, r3, #1 800163a: 6213 str r3, [r2, #32] 800163c: e00b b.n 8001656 800163e: 4b5b ldr r3, [pc, #364] @ (80017ac ) 8001640: 6a1b ldr r3, [r3, #32] 8001642: 4a5a ldr r2, [pc, #360] @ (80017ac ) 8001644: f023 0301 bic.w r3, r3, #1 8001648: 6213 str r3, [r2, #32] 800164a: 4b58 ldr r3, [pc, #352] @ (80017ac ) 800164c: 6a1b ldr r3, [r3, #32] 800164e: 4a57 ldr r2, [pc, #348] @ (80017ac ) 8001650: f023 0304 bic.w r3, r3, #4 8001654: 6213 str r3, [r2, #32] /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8001656: 687b ldr r3, [r7, #4] 8001658: 68db ldr r3, [r3, #12] 800165a: 2b00 cmp r3, #0 800165c: d015 beq.n 800168a { /* Get Start Tick */ tickstart = HAL_GetTick(); 800165e: f7ff f9cd bl 80009fc 8001662: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8001664: e00a b.n 800167c { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8001666: f7ff f9c9 bl 80009fc 800166a: 4602 mov r2, r0 800166c: 693b ldr r3, [r7, #16] 800166e: 1ad3 subs r3, r2, r3 8001670: f241 3288 movw r2, #5000 @ 0x1388 8001674: 4293 cmp r3, r2 8001676: d901 bls.n 800167c { return HAL_TIMEOUT; 8001678: 2303 movs r3, #3 800167a: e0b1 b.n 80017e0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 800167c: 4b4b ldr r3, [pc, #300] @ (80017ac ) 800167e: 6a1b ldr r3, [r3, #32] 8001680: f003 0302 and.w r3, r3, #2 8001684: 2b00 cmp r3, #0 8001686: d0ee beq.n 8001666 8001688: e014 b.n 80016b4 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 800168a: f7ff f9b7 bl 80009fc 800168e: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8001690: e00a b.n 80016a8 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8001692: f7ff f9b3 bl 80009fc 8001696: 4602 mov r2, r0 8001698: 693b ldr r3, [r7, #16] 800169a: 1ad3 subs r3, r2, r3 800169c: f241 3288 movw r2, #5000 @ 0x1388 80016a0: 4293 cmp r3, r2 80016a2: d901 bls.n 80016a8 { return HAL_TIMEOUT; 80016a4: 2303 movs r3, #3 80016a6: e09b b.n 80017e0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 80016a8: 4b40 ldr r3, [pc, #256] @ (80017ac ) 80016aa: 6a1b ldr r3, [r3, #32] 80016ac: f003 0302 and.w r3, r3, #2 80016b0: 2b00 cmp r3, #0 80016b2: d1ee bne.n 8001692 } } } /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 80016b4: 7dfb ldrb r3, [r7, #23] 80016b6: 2b01 cmp r3, #1 80016b8: d105 bne.n 80016c6 { __HAL_RCC_PWR_CLK_DISABLE(); 80016ba: 4b3c ldr r3, [pc, #240] @ (80017ac ) 80016bc: 69db ldr r3, [r3, #28] 80016be: 4a3b ldr r2, [pc, #236] @ (80017ac ) 80016c0: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 80016c4: 61d3 str r3, [r2, #28] #endif /* RCC_CR_PLL2ON */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 80016c6: 687b ldr r3, [r7, #4] 80016c8: 69db ldr r3, [r3, #28] 80016ca: 2b00 cmp r3, #0 80016cc: f000 8087 beq.w 80017de { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 80016d0: 4b36 ldr r3, [pc, #216] @ (80017ac ) 80016d2: 685b ldr r3, [r3, #4] 80016d4: f003 030c and.w r3, r3, #12 80016d8: 2b08 cmp r3, #8 80016da: d061 beq.n 80017a0 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 80016dc: 687b ldr r3, [r7, #4] 80016de: 69db ldr r3, [r3, #28] 80016e0: 2b02 cmp r3, #2 80016e2: d146 bne.n 8001772 /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80016e4: 4b33 ldr r3, [pc, #204] @ (80017b4 ) 80016e6: 2200 movs r2, #0 80016e8: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80016ea: f7ff f987 bl 80009fc 80016ee: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80016f0: e008 b.n 8001704 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80016f2: f7ff f983 bl 80009fc 80016f6: 4602 mov r2, r0 80016f8: 693b ldr r3, [r7, #16] 80016fa: 1ad3 subs r3, r2, r3 80016fc: 2b02 cmp r3, #2 80016fe: d901 bls.n 8001704 { return HAL_TIMEOUT; 8001700: 2303 movs r3, #3 8001702: e06d b.n 80017e0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8001704: 4b29 ldr r3, [pc, #164] @ (80017ac ) 8001706: 681b ldr r3, [r3, #0] 8001708: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800170c: 2b00 cmp r3, #0 800170e: d1f0 bne.n 80016f2 } } /* Configure the HSE prediv factor --------------------------------*/ /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) 8001710: 687b ldr r3, [r7, #4] 8001712: 6a1b ldr r3, [r3, #32] 8001714: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8001718: d108 bne.n 800172c /* Set PREDIV1 source */ SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); #endif /* RCC_CFGR2_PREDIV1SRC */ /* Set PREDIV1 Value */ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); 800171a: 4b24 ldr r3, [pc, #144] @ (80017ac ) 800171c: 685b ldr r3, [r3, #4] 800171e: f423 3200 bic.w r2, r3, #131072 @ 0x20000 8001722: 687b ldr r3, [r7, #4] 8001724: 689b ldr r3, [r3, #8] 8001726: 4921 ldr r1, [pc, #132] @ (80017ac ) 8001728: 4313 orrs r3, r2 800172a: 604b str r3, [r1, #4] } /* Configure the main PLL clock source and multiplication factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 800172c: 4b1f ldr r3, [pc, #124] @ (80017ac ) 800172e: 685b ldr r3, [r3, #4] 8001730: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000 8001734: 687b ldr r3, [r7, #4] 8001736: 6a19 ldr r1, [r3, #32] 8001738: 687b ldr r3, [r7, #4] 800173a: 6a5b ldr r3, [r3, #36] @ 0x24 800173c: 430b orrs r3, r1 800173e: 491b ldr r1, [pc, #108] @ (80017ac ) 8001740: 4313 orrs r3, r2 8001742: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8001744: 4b1b ldr r3, [pc, #108] @ (80017b4 ) 8001746: 2201 movs r2, #1 8001748: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800174a: f7ff f957 bl 80009fc 800174e: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8001750: e008 b.n 8001764 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8001752: f7ff f953 bl 80009fc 8001756: 4602 mov r2, r0 8001758: 693b ldr r3, [r7, #16] 800175a: 1ad3 subs r3, r2, r3 800175c: 2b02 cmp r3, #2 800175e: d901 bls.n 8001764 { return HAL_TIMEOUT; 8001760: 2303 movs r3, #3 8001762: e03d b.n 80017e0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8001764: 4b11 ldr r3, [pc, #68] @ (80017ac ) 8001766: 681b ldr r3, [r3, #0] 8001768: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800176c: 2b00 cmp r3, #0 800176e: d0f0 beq.n 8001752 8001770: e035 b.n 80017de } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8001772: 4b10 ldr r3, [pc, #64] @ (80017b4 ) 8001774: 2200 movs r2, #0 8001776: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001778: f7ff f940 bl 80009fc 800177c: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 800177e: e008 b.n 8001792 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8001780: f7ff f93c bl 80009fc 8001784: 4602 mov r2, r0 8001786: 693b ldr r3, [r7, #16] 8001788: 1ad3 subs r3, r2, r3 800178a: 2b02 cmp r3, #2 800178c: d901 bls.n 8001792 { return HAL_TIMEOUT; 800178e: 2303 movs r3, #3 8001790: e026 b.n 80017e0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8001792: 4b06 ldr r3, [pc, #24] @ (80017ac ) 8001794: 681b ldr r3, [r3, #0] 8001796: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800179a: 2b00 cmp r3, #0 800179c: d1f0 bne.n 8001780 800179e: e01e b.n 80017de } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 80017a0: 687b ldr r3, [r7, #4] 80017a2: 69db ldr r3, [r3, #28] 80017a4: 2b01 cmp r3, #1 80017a6: d107 bne.n 80017b8 { return HAL_ERROR; 80017a8: 2301 movs r3, #1 80017aa: e019 b.n 80017e0 80017ac: 40021000 .word 0x40021000 80017b0: 40007000 .word 0x40007000 80017b4: 42420060 .word 0x42420060 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 80017b8: 4b0b ldr r3, [pc, #44] @ (80017e8 ) 80017ba: 685b ldr r3, [r3, #4] 80017bc: 60fb str r3, [r7, #12] if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80017be: 68fb ldr r3, [r7, #12] 80017c0: f403 3280 and.w r2, r3, #65536 @ 0x10000 80017c4: 687b ldr r3, [r7, #4] 80017c6: 6a1b ldr r3, [r3, #32] 80017c8: 429a cmp r2, r3 80017ca: d106 bne.n 80017da (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL)) 80017cc: 68fb ldr r3, [r7, #12] 80017ce: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000 80017d2: 687b ldr r3, [r7, #4] 80017d4: 6a5b ldr r3, [r3, #36] @ 0x24 if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80017d6: 429a cmp r2, r3 80017d8: d001 beq.n 80017de { return HAL_ERROR; 80017da: 2301 movs r3, #1 80017dc: e000 b.n 80017e0 } } } } return HAL_OK; 80017de: 2300 movs r3, #0 } 80017e0: 4618 mov r0, r3 80017e2: 3718 adds r7, #24 80017e4: 46bd mov sp, r7 80017e6: bd80 pop {r7, pc} 80017e8: 40021000 .word 0x40021000 080017ec : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 80017ec: b580 push {r7, lr} 80017ee: b084 sub sp, #16 80017f0: af00 add r7, sp, #0 80017f2: 6078 str r0, [r7, #4] 80017f4: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 80017f6: 687b ldr r3, [r7, #4] 80017f8: 2b00 cmp r3, #0 80017fa: d101 bne.n 8001800 { return HAL_ERROR; 80017fc: 2301 movs r3, #1 80017fe: e0d0 b.n 80019a2 must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ #if defined(FLASH_ACR_LATENCY) /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 8001800: 4b6a ldr r3, [pc, #424] @ (80019ac ) 8001802: 681b ldr r3, [r3, #0] 8001804: f003 0307 and.w r3, r3, #7 8001808: 683a ldr r2, [r7, #0] 800180a: 429a cmp r2, r3 800180c: d910 bls.n 8001830 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800180e: 4b67 ldr r3, [pc, #412] @ (80019ac ) 8001810: 681b ldr r3, [r3, #0] 8001812: f023 0207 bic.w r2, r3, #7 8001816: 4965 ldr r1, [pc, #404] @ (80019ac ) 8001818: 683b ldr r3, [r7, #0] 800181a: 4313 orrs r3, r2 800181c: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 800181e: 4b63 ldr r3, [pc, #396] @ (80019ac ) 8001820: 681b ldr r3, [r3, #0] 8001822: f003 0307 and.w r3, r3, #7 8001826: 683a ldr r2, [r7, #0] 8001828: 429a cmp r2, r3 800182a: d001 beq.n 8001830 { return HAL_ERROR; 800182c: 2301 movs r3, #1 800182e: e0b8 b.n 80019a2 } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8001830: 687b ldr r3, [r7, #4] 8001832: 681b ldr r3, [r3, #0] 8001834: f003 0302 and.w r3, r3, #2 8001838: 2b00 cmp r3, #0 800183a: d020 beq.n 800187e { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800183c: 687b ldr r3, [r7, #4] 800183e: 681b ldr r3, [r3, #0] 8001840: f003 0304 and.w r3, r3, #4 8001844: 2b00 cmp r3, #0 8001846: d005 beq.n 8001854 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8001848: 4b59 ldr r3, [pc, #356] @ (80019b0 ) 800184a: 685b ldr r3, [r3, #4] 800184c: 4a58 ldr r2, [pc, #352] @ (80019b0 ) 800184e: f443 63e0 orr.w r3, r3, #1792 @ 0x700 8001852: 6053 str r3, [r2, #4] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8001854: 687b ldr r3, [r7, #4] 8001856: 681b ldr r3, [r3, #0] 8001858: f003 0308 and.w r3, r3, #8 800185c: 2b00 cmp r3, #0 800185e: d005 beq.n 800186c { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 8001860: 4b53 ldr r3, [pc, #332] @ (80019b0 ) 8001862: 685b ldr r3, [r3, #4] 8001864: 4a52 ldr r2, [pc, #328] @ (80019b0 ) 8001866: f443 5360 orr.w r3, r3, #14336 @ 0x3800 800186a: 6053 str r3, [r2, #4] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 800186c: 4b50 ldr r3, [pc, #320] @ (80019b0 ) 800186e: 685b ldr r3, [r3, #4] 8001870: f023 02f0 bic.w r2, r3, #240 @ 0xf0 8001874: 687b ldr r3, [r7, #4] 8001876: 689b ldr r3, [r3, #8] 8001878: 494d ldr r1, [pc, #308] @ (80019b0 ) 800187a: 4313 orrs r3, r2 800187c: 604b str r3, [r1, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 800187e: 687b ldr r3, [r7, #4] 8001880: 681b ldr r3, [r3, #0] 8001882: f003 0301 and.w r3, r3, #1 8001886: 2b00 cmp r3, #0 8001888: d040 beq.n 800190c { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 800188a: 687b ldr r3, [r7, #4] 800188c: 685b ldr r3, [r3, #4] 800188e: 2b01 cmp r3, #1 8001890: d107 bne.n 80018a2 { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8001892: 4b47 ldr r3, [pc, #284] @ (80019b0 ) 8001894: 681b ldr r3, [r3, #0] 8001896: f403 3300 and.w r3, r3, #131072 @ 0x20000 800189a: 2b00 cmp r3, #0 800189c: d115 bne.n 80018ca { return HAL_ERROR; 800189e: 2301 movs r3, #1 80018a0: e07f b.n 80019a2 } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 80018a2: 687b ldr r3, [r7, #4] 80018a4: 685b ldr r3, [r3, #4] 80018a6: 2b02 cmp r3, #2 80018a8: d107 bne.n 80018ba { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80018aa: 4b41 ldr r3, [pc, #260] @ (80019b0 ) 80018ac: 681b ldr r3, [r3, #0] 80018ae: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80018b2: 2b00 cmp r3, #0 80018b4: d109 bne.n 80018ca { return HAL_ERROR; 80018b6: 2301 movs r3, #1 80018b8: e073 b.n 80019a2 } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80018ba: 4b3d ldr r3, [pc, #244] @ (80019b0 ) 80018bc: 681b ldr r3, [r3, #0] 80018be: f003 0302 and.w r3, r3, #2 80018c2: 2b00 cmp r3, #0 80018c4: d101 bne.n 80018ca { return HAL_ERROR; 80018c6: 2301 movs r3, #1 80018c8: e06b b.n 80019a2 } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 80018ca: 4b39 ldr r3, [pc, #228] @ (80019b0 ) 80018cc: 685b ldr r3, [r3, #4] 80018ce: f023 0203 bic.w r2, r3, #3 80018d2: 687b ldr r3, [r7, #4] 80018d4: 685b ldr r3, [r3, #4] 80018d6: 4936 ldr r1, [pc, #216] @ (80019b0 ) 80018d8: 4313 orrs r3, r2 80018da: 604b str r3, [r1, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 80018dc: f7ff f88e bl 80009fc 80018e0: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80018e2: e00a b.n 80018fa { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 80018e4: f7ff f88a bl 80009fc 80018e8: 4602 mov r2, r0 80018ea: 68fb ldr r3, [r7, #12] 80018ec: 1ad3 subs r3, r2, r3 80018ee: f241 3288 movw r2, #5000 @ 0x1388 80018f2: 4293 cmp r3, r2 80018f4: d901 bls.n 80018fa { return HAL_TIMEOUT; 80018f6: 2303 movs r3, #3 80018f8: e053 b.n 80019a2 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80018fa: 4b2d ldr r3, [pc, #180] @ (80019b0 ) 80018fc: 685b ldr r3, [r3, #4] 80018fe: f003 020c and.w r2, r3, #12 8001902: 687b ldr r3, [r7, #4] 8001904: 685b ldr r3, [r3, #4] 8001906: 009b lsls r3, r3, #2 8001908: 429a cmp r2, r3 800190a: d1eb bne.n 80018e4 } } #if defined(FLASH_ACR_LATENCY) /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 800190c: 4b27 ldr r3, [pc, #156] @ (80019ac ) 800190e: 681b ldr r3, [r3, #0] 8001910: f003 0307 and.w r3, r3, #7 8001914: 683a ldr r2, [r7, #0] 8001916: 429a cmp r2, r3 8001918: d210 bcs.n 800193c { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800191a: 4b24 ldr r3, [pc, #144] @ (80019ac ) 800191c: 681b ldr r3, [r3, #0] 800191e: f023 0207 bic.w r2, r3, #7 8001922: 4922 ldr r1, [pc, #136] @ (80019ac ) 8001924: 683b ldr r3, [r7, #0] 8001926: 4313 orrs r3, r2 8001928: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 800192a: 4b20 ldr r3, [pc, #128] @ (80019ac ) 800192c: 681b ldr r3, [r3, #0] 800192e: f003 0307 and.w r3, r3, #7 8001932: 683a ldr r2, [r7, #0] 8001934: 429a cmp r2, r3 8001936: d001 beq.n 800193c { return HAL_ERROR; 8001938: 2301 movs r3, #1 800193a: e032 b.n 80019a2 } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800193c: 687b ldr r3, [r7, #4] 800193e: 681b ldr r3, [r3, #0] 8001940: f003 0304 and.w r3, r3, #4 8001944: 2b00 cmp r3, #0 8001946: d008 beq.n 800195a { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8001948: 4b19 ldr r3, [pc, #100] @ (80019b0 ) 800194a: 685b ldr r3, [r3, #4] 800194c: f423 62e0 bic.w r2, r3, #1792 @ 0x700 8001950: 687b ldr r3, [r7, #4] 8001952: 68db ldr r3, [r3, #12] 8001954: 4916 ldr r1, [pc, #88] @ (80019b0 ) 8001956: 4313 orrs r3, r2 8001958: 604b str r3, [r1, #4] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 800195a: 687b ldr r3, [r7, #4] 800195c: 681b ldr r3, [r3, #0] 800195e: f003 0308 and.w r3, r3, #8 8001962: 2b00 cmp r3, #0 8001964: d009 beq.n 800197a { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); 8001966: 4b12 ldr r3, [pc, #72] @ (80019b0 ) 8001968: 685b ldr r3, [r3, #4] 800196a: f423 5260 bic.w r2, r3, #14336 @ 0x3800 800196e: 687b ldr r3, [r7, #4] 8001970: 691b ldr r3, [r3, #16] 8001972: 00db lsls r3, r3, #3 8001974: 490e ldr r1, [pc, #56] @ (80019b0 ) 8001976: 4313 orrs r3, r2 8001978: 604b str r3, [r1, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 800197a: f000 f821 bl 80019c0 800197e: 4602 mov r2, r0 8001980: 4b0b ldr r3, [pc, #44] @ (80019b0 ) 8001982: 685b ldr r3, [r3, #4] 8001984: 091b lsrs r3, r3, #4 8001986: f003 030f and.w r3, r3, #15 800198a: 490a ldr r1, [pc, #40] @ (80019b4 ) 800198c: 5ccb ldrb r3, [r1, r3] 800198e: fa22 f303 lsr.w r3, r2, r3 8001992: 4a09 ldr r2, [pc, #36] @ (80019b8 ) 8001994: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick(uwTickPrio); 8001996: 4b09 ldr r3, [pc, #36] @ (80019bc ) 8001998: 681b ldr r3, [r3, #0] 800199a: 4618 mov r0, r3 800199c: f7fe ffec bl 8000978 return HAL_OK; 80019a0: 2300 movs r3, #0 } 80019a2: 4618 mov r0, r3 80019a4: 3710 adds r7, #16 80019a6: 46bd mov sp, r7 80019a8: bd80 pop {r7, pc} 80019aa: bf00 nop 80019ac: 40022000 .word 0x40022000 80019b0: 40021000 .word 0x40021000 80019b4: 08004330 .word 0x08004330 80019b8: 20000000 .word 0x20000000 80019bc: 20000004 .word 0x20000004 080019c0 : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 80019c0: b480 push {r7} 80019c2: b087 sub sp, #28 80019c4: af00 add r7, sp, #0 #else static const uint8_t aPredivFactorTable[2U] = {1, 2}; #endif /*RCC_CFGR2_PREDIV1*/ #endif uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 80019c6: 2300 movs r3, #0 80019c8: 60fb str r3, [r7, #12] 80019ca: 2300 movs r3, #0 80019cc: 60bb str r3, [r7, #8] 80019ce: 2300 movs r3, #0 80019d0: 617b str r3, [r7, #20] 80019d2: 2300 movs r3, #0 80019d4: 607b str r3, [r7, #4] uint32_t sysclockfreq = 0U; 80019d6: 2300 movs r3, #0 80019d8: 613b str r3, [r7, #16] #if defined(RCC_CFGR2_PREDIV1SRC) uint32_t prediv2 = 0U, pll2mul = 0U; #endif /*RCC_CFGR2_PREDIV1SRC*/ tmpreg = RCC->CFGR; 80019da: 4b1e ldr r3, [pc, #120] @ (8001a54 ) 80019dc: 685b ldr r3, [r3, #4] 80019de: 60fb str r3, [r7, #12] /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 80019e0: 68fb ldr r3, [r7, #12] 80019e2: f003 030c and.w r3, r3, #12 80019e6: 2b04 cmp r3, #4 80019e8: d002 beq.n 80019f0 80019ea: 2b08 cmp r3, #8 80019ec: d003 beq.n 80019f6 80019ee: e027 b.n 8001a40 { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 80019f0: 4b19 ldr r3, [pc, #100] @ (8001a58 ) 80019f2: 613b str r3, [r7, #16] break; 80019f4: e027 b.n 8001a46 } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 80019f6: 68fb ldr r3, [r7, #12] 80019f8: 0c9b lsrs r3, r3, #18 80019fa: f003 030f and.w r3, r3, #15 80019fe: 4a17 ldr r2, [pc, #92] @ (8001a5c ) 8001a00: 5cd3 ldrb r3, [r2, r3] 8001a02: 607b str r3, [r7, #4] if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 8001a04: 68fb ldr r3, [r7, #12] 8001a06: f403 3380 and.w r3, r3, #65536 @ 0x10000 8001a0a: 2b00 cmp r3, #0 8001a0c: d010 beq.n 8001a30 { #if defined(RCC_CFGR2_PREDIV1) prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; #else prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; 8001a0e: 4b11 ldr r3, [pc, #68] @ (8001a54 ) 8001a10: 685b ldr r3, [r3, #4] 8001a12: 0c5b lsrs r3, r3, #17 8001a14: f003 0301 and.w r3, r3, #1 8001a18: 4a11 ldr r2, [pc, #68] @ (8001a60 ) 8001a1a: 5cd3 ldrb r3, [r2, r3] 8001a1c: 60bb str r3, [r7, #8] { pllclk = pllclk / 2; } #else /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); 8001a1e: 687b ldr r3, [r7, #4] 8001a20: 4a0d ldr r2, [pc, #52] @ (8001a58 ) 8001a22: fb03 f202 mul.w r2, r3, r2 8001a26: 68bb ldr r3, [r7, #8] 8001a28: fbb2 f3f3 udiv r3, r2, r3 8001a2c: 617b str r3, [r7, #20] 8001a2e: e004 b.n 8001a3a #endif /*RCC_CFGR2_PREDIV1SRC*/ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 8001a30: 687b ldr r3, [r7, #4] 8001a32: 4a0c ldr r2, [pc, #48] @ (8001a64 ) 8001a34: fb02 f303 mul.w r3, r2, r3 8001a38: 617b str r3, [r7, #20] } sysclockfreq = pllclk; 8001a3a: 697b ldr r3, [r7, #20] 8001a3c: 613b str r3, [r7, #16] break; 8001a3e: e002 b.n 8001a46 } case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 8001a40: 4b09 ldr r3, [pc, #36] @ (8001a68 ) 8001a42: 613b str r3, [r7, #16] break; 8001a44: bf00 nop } } return sysclockfreq; 8001a46: 693b ldr r3, [r7, #16] } 8001a48: 4618 mov r0, r3 8001a4a: 371c adds r7, #28 8001a4c: 46bd mov sp, r7 8001a4e: bc80 pop {r7} 8001a50: 4770 bx lr 8001a52: bf00 nop 8001a54: 40021000 .word 0x40021000 8001a58: 00f42400 .word 0x00f42400 8001a5c: 08004348 .word 0x08004348 8001a60: 08004358 .word 0x08004358 8001a64: 003d0900 .word 0x003d0900 8001a68: 007a1200 .word 0x007a1200 08001a6c : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8001a6c: b480 push {r7} 8001a6e: af00 add r7, sp, #0 return SystemCoreClock; 8001a70: 4b02 ldr r3, [pc, #8] @ (8001a7c ) 8001a72: 681b ldr r3, [r3, #0] } 8001a74: 4618 mov r0, r3 8001a76: 46bd mov sp, r7 8001a78: bc80 pop {r7} 8001a7a: 4770 bx lr 8001a7c: 20000000 .word 0x20000000 08001a80 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8001a80: b580 push {r7, lr} 8001a82: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 8001a84: f7ff fff2 bl 8001a6c 8001a88: 4602 mov r2, r0 8001a8a: 4b05 ldr r3, [pc, #20] @ (8001aa0 ) 8001a8c: 685b ldr r3, [r3, #4] 8001a8e: 0a1b lsrs r3, r3, #8 8001a90: f003 0307 and.w r3, r3, #7 8001a94: 4903 ldr r1, [pc, #12] @ (8001aa4 ) 8001a96: 5ccb ldrb r3, [r1, r3] 8001a98: fa22 f303 lsr.w r3, r2, r3 } 8001a9c: 4618 mov r0, r3 8001a9e: bd80 pop {r7, pc} 8001aa0: 40021000 .word 0x40021000 8001aa4: 08004340 .word 0x08004340 08001aa8 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 8001aa8: b580 push {r7, lr} 8001aaa: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 8001aac: f7ff ffde bl 8001a6c 8001ab0: 4602 mov r2, r0 8001ab2: 4b05 ldr r3, [pc, #20] @ (8001ac8 ) 8001ab4: 685b ldr r3, [r3, #4] 8001ab6: 0adb lsrs r3, r3, #11 8001ab8: f003 0307 and.w r3, r3, #7 8001abc: 4903 ldr r1, [pc, #12] @ (8001acc ) 8001abe: 5ccb ldrb r3, [r1, r3] 8001ac0: fa22 f303 lsr.w r3, r2, r3 } 8001ac4: 4618 mov r0, r3 8001ac6: bd80 pop {r7, pc} 8001ac8: 40021000 .word 0x40021000 8001acc: 08004340 .word 0x08004340 08001ad0 : * @brief This function provides delay (in milliseconds) based on CPU cycles method. * @param mdelay: specifies the delay time length, in milliseconds. * @retval None */ static void RCC_Delay(uint32_t mdelay) { 8001ad0: b480 push {r7} 8001ad2: b085 sub sp, #20 8001ad4: af00 add r7, sp, #0 8001ad6: 6078 str r0, [r7, #4] __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); 8001ad8: 4b0a ldr r3, [pc, #40] @ (8001b04 ) 8001ada: 681b ldr r3, [r3, #0] 8001adc: 4a0a ldr r2, [pc, #40] @ (8001b08 ) 8001ade: fba2 2303 umull r2, r3, r2, r3 8001ae2: 0a5b lsrs r3, r3, #9 8001ae4: 687a ldr r2, [r7, #4] 8001ae6: fb02 f303 mul.w r3, r2, r3 8001aea: 60fb str r3, [r7, #12] do { __NOP(); 8001aec: bf00 nop } while (Delay --); 8001aee: 68fb ldr r3, [r7, #12] 8001af0: 1e5a subs r2, r3, #1 8001af2: 60fa str r2, [r7, #12] 8001af4: 2b00 cmp r3, #0 8001af6: d1f9 bne.n 8001aec } 8001af8: bf00 nop 8001afa: bf00 nop 8001afc: 3714 adds r7, #20 8001afe: 46bd mov sp, r7 8001b00: bc80 pop {r7} 8001b02: 4770 bx lr 8001b04: 20000000 .word 0x20000000 8001b08: 10624dd3 .word 0x10624dd3 08001b0c : SD_HandleTypeDef and create the associated handle. * @param hsd: Pointer to the SD handle * @retval HAL status */ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) { 8001b0c: b580 push {r7, lr} 8001b0e: b082 sub sp, #8 8001b10: af00 add r7, sp, #0 8001b12: 6078 str r0, [r7, #4] /* Check the SD handle allocation */ if(hsd == NULL) 8001b14: 687b ldr r3, [r7, #4] 8001b16: 2b00 cmp r3, #0 8001b18: d101 bne.n 8001b1e { return HAL_ERROR; 8001b1a: 2301 movs r3, #1 8001b1c: e022 b.n 8001b64 assert_param(IS_SDIO_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave)); assert_param(IS_SDIO_BUS_WIDE(hsd->Init.BusWide)); assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl)); assert_param(IS_SDIO_CLKDIV(hsd->Init.ClockDiv)); if(hsd->State == HAL_SD_STATE_RESET) 8001b1e: 687b ldr r3, [r7, #4] 8001b20: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 8001b24: b2db uxtb r3, r3 8001b26: 2b00 cmp r3, #0 8001b28: d105 bne.n 8001b36 { /* Allocate lock resource and initialize it */ hsd->Lock = HAL_UNLOCKED; 8001b2a: 687b ldr r3, [r7, #4] 8001b2c: 2200 movs r2, #0 8001b2e: 771a strb r2, [r3, #28] /* Init the low level hardware */ hsd->MspInitCallback(hsd); #else /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ HAL_SD_MspInit(hsd); 8001b30: 6878 ldr r0, [r7, #4] 8001b32: f7fe fd63 bl 80005fc #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } hsd->State = HAL_SD_STATE_BUSY; 8001b36: 687b ldr r3, [r7, #4] 8001b38: 2203 movs r2, #3 8001b3a: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Initialize the Card parameters */ if (HAL_SD_InitCard(hsd) != HAL_OK) 8001b3e: 6878 ldr r0, [r7, #4] 8001b40: f000 f814 bl 8001b6c 8001b44: 4603 mov r3, r0 8001b46: 2b00 cmp r3, #0 8001b48: d001 beq.n 8001b4e { return HAL_ERROR; 8001b4a: 2301 movs r3, #1 8001b4c: e00a b.n 8001b64 } /* Initialize the error code */ hsd->ErrorCode = HAL_SD_ERROR_NONE; 8001b4e: 687b ldr r3, [r7, #4] 8001b50: 2200 movs r2, #0 8001b52: 639a str r2, [r3, #56] @ 0x38 /* Initialize the SD operation */ hsd->Context = SD_CONTEXT_NONE; 8001b54: 687b ldr r3, [r7, #4] 8001b56: 2200 movs r2, #0 8001b58: 631a str r2, [r3, #48] @ 0x30 /* Initialize the SD state */ hsd->State = HAL_SD_STATE_READY; 8001b5a: 687b ldr r3, [r7, #4] 8001b5c: 2201 movs r2, #1 8001b5e: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_OK; 8001b62: 2300 movs r3, #0 } 8001b64: 4618 mov r0, r3 8001b66: 3708 adds r7, #8 8001b68: 46bd mov sp, r7 8001b6a: bd80 pop {r7, pc} 08001b6c : * @note This function initializes the SD card. It could be used when a card re-initialization is needed. * @retval HAL status */ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) { 8001b6c: b5b0 push {r4, r5, r7, lr} 8001b6e: b08e sub sp, #56 @ 0x38 8001b70: af04 add r7, sp, #16 8001b72: 6078 str r0, [r7, #4] uint32_t errorstate; SD_InitTypeDef Init; /* Default SDIO peripheral configuration for SD card initialization */ Init.ClockEdge = SDIO_CLOCK_EDGE_RISING; 8001b74: 2300 movs r3, #0 8001b76: 60fb str r3, [r7, #12] Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE; 8001b78: 2300 movs r3, #0 8001b7a: 613b str r3, [r7, #16] Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; 8001b7c: 2300 movs r3, #0 8001b7e: 617b str r3, [r7, #20] Init.BusWide = SDIO_BUS_WIDE_1B; 8001b80: 2300 movs r3, #0 8001b82: 61bb str r3, [r7, #24] Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; 8001b84: 2300 movs r3, #0 8001b86: 61fb str r3, [r7, #28] Init.ClockDiv = SDIO_INIT_CLK_DIV; 8001b88: 2376 movs r3, #118 @ 0x76 8001b8a: 623b str r3, [r7, #32] /* Initialize SDIO peripheral interface with default configuration */ SDIO_Init(hsd->Instance, Init); 8001b8c: 687b ldr r3, [r7, #4] 8001b8e: 681d ldr r5, [r3, #0] 8001b90: 466c mov r4, sp 8001b92: f107 0318 add.w r3, r7, #24 8001b96: e893 0007 ldmia.w r3, {r0, r1, r2} 8001b9a: e884 0007 stmia.w r4, {r0, r1, r2} 8001b9e: f107 030c add.w r3, r7, #12 8001ba2: cb0e ldmia r3, {r1, r2, r3} 8001ba4: 4628 mov r0, r5 8001ba6: f001 fc73 bl 8003490 /* Disable SDIO Clock */ __HAL_SD_DISABLE(hsd); 8001baa: 4b2a ldr r3, [pc, #168] @ (8001c54 ) 8001bac: 2200 movs r2, #0 8001bae: 601a str r2, [r3, #0] /* Set Power State to ON */ (void)SDIO_PowerState_ON(hsd->Instance); 8001bb0: 687b ldr r3, [r7, #4] 8001bb2: 681b ldr r3, [r3, #0] 8001bb4: 4618 mov r0, r3 8001bb6: f001 fcb1 bl 800351c /* Enable SDIO Clock */ __HAL_SD_ENABLE(hsd); 8001bba: 4b26 ldr r3, [pc, #152] @ (8001c54 ) 8001bbc: 2201 movs r2, #1 8001bbe: 601a str r2, [r3, #0] /* Required power up waiting time before starting the SD initialization sequence */ HAL_Delay(2); 8001bc0: 2002 movs r0, #2 8001bc2: f7fe ff25 bl 8000a10 /* Identify card operating voltage */ errorstate = SD_PowerON(hsd); 8001bc6: 6878 ldr r0, [r7, #4] 8001bc8: f000 fe7a bl 80028c0 8001bcc: 6278 str r0, [r7, #36] @ 0x24 if(errorstate != HAL_SD_ERROR_NONE) 8001bce: 6a7b ldr r3, [r7, #36] @ 0x24 8001bd0: 2b00 cmp r3, #0 8001bd2: d00b beq.n 8001bec { hsd->State = HAL_SD_STATE_READY; 8001bd4: 687b ldr r3, [r7, #4] 8001bd6: 2201 movs r2, #1 8001bd8: f883 2034 strb.w r2, [r3, #52] @ 0x34 hsd->ErrorCode |= errorstate; 8001bdc: 687b ldr r3, [r7, #4] 8001bde: 6b9a ldr r2, [r3, #56] @ 0x38 8001be0: 6a7b ldr r3, [r7, #36] @ 0x24 8001be2: 431a orrs r2, r3 8001be4: 687b ldr r3, [r7, #4] 8001be6: 639a str r2, [r3, #56] @ 0x38 return HAL_ERROR; 8001be8: 2301 movs r3, #1 8001bea: e02e b.n 8001c4a } /* Card initialization */ errorstate = SD_InitCard(hsd); 8001bec: 6878 ldr r0, [r7, #4] 8001bee: f000 fd98 bl 8002722 8001bf2: 6278 str r0, [r7, #36] @ 0x24 if(errorstate != HAL_SD_ERROR_NONE) 8001bf4: 6a7b ldr r3, [r7, #36] @ 0x24 8001bf6: 2b00 cmp r3, #0 8001bf8: d00b beq.n 8001c12 { hsd->State = HAL_SD_STATE_READY; 8001bfa: 687b ldr r3, [r7, #4] 8001bfc: 2201 movs r2, #1 8001bfe: f883 2034 strb.w r2, [r3, #52] @ 0x34 hsd->ErrorCode |= errorstate; 8001c02: 687b ldr r3, [r7, #4] 8001c04: 6b9a ldr r2, [r3, #56] @ 0x38 8001c06: 6a7b ldr r3, [r7, #36] @ 0x24 8001c08: 431a orrs r2, r3 8001c0a: 687b ldr r3, [r7, #4] 8001c0c: 639a str r2, [r3, #56] @ 0x38 return HAL_ERROR; 8001c0e: 2301 movs r3, #1 8001c10: e01b b.n 8001c4a } /* Set Block Size for Card */ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); 8001c12: 687b ldr r3, [r7, #4] 8001c14: 681b ldr r3, [r3, #0] 8001c16: f44f 7100 mov.w r1, #512 @ 0x200 8001c1a: 4618 mov r0, r3 8001c1c: f001 fd0a bl 8003634 8001c20: 6278 str r0, [r7, #36] @ 0x24 if(errorstate != HAL_SD_ERROR_NONE) 8001c22: 6a7b ldr r3, [r7, #36] @ 0x24 8001c24: 2b00 cmp r3, #0 8001c26: d00f beq.n 8001c48 { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); 8001c28: 687b ldr r3, [r7, #4] 8001c2a: 681b ldr r3, [r3, #0] 8001c2c: 4a0a ldr r2, [pc, #40] @ (8001c58 ) 8001c2e: 639a str r2, [r3, #56] @ 0x38 hsd->ErrorCode |= errorstate; 8001c30: 687b ldr r3, [r7, #4] 8001c32: 6b9a ldr r2, [r3, #56] @ 0x38 8001c34: 6a7b ldr r3, [r7, #36] @ 0x24 8001c36: 431a orrs r2, r3 8001c38: 687b ldr r3, [r7, #4] 8001c3a: 639a str r2, [r3, #56] @ 0x38 hsd->State = HAL_SD_STATE_READY; 8001c3c: 687b ldr r3, [r7, #4] 8001c3e: 2201 movs r2, #1 8001c40: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_ERROR; 8001c44: 2301 movs r3, #1 8001c46: e000 b.n 8001c4a } return HAL_OK; 8001c48: 2300 movs r3, #0 } 8001c4a: 4618 mov r0, r3 8001c4c: 3728 adds r7, #40 @ 0x28 8001c4e: 46bd mov sp, r7 8001c50: bdb0 pop {r4, r5, r7, pc} 8001c52: bf00 nop 8001c54: 423000a0 .word 0x423000a0 8001c58: 004005ff .word 0x004005ff 08001c5c : * @param NumberOfBlocks: Number of SD blocks to read * @param Timeout: Specify timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) { 8001c5c: b580 push {r7, lr} 8001c5e: b092 sub sp, #72 @ 0x48 8001c60: af00 add r7, sp, #0 8001c62: 60f8 str r0, [r7, #12] 8001c64: 60b9 str r1, [r7, #8] 8001c66: 607a str r2, [r7, #4] 8001c68: 603b str r3, [r7, #0] SDIO_DataInitTypeDef config; uint32_t errorstate; uint32_t tickstart = HAL_GetTick(); 8001c6a: f7fe fec7 bl 80009fc 8001c6e: 6338 str r0, [r7, #48] @ 0x30 uint32_t count, data, dataremaining; uint32_t add = BlockAdd; 8001c70: 687b ldr r3, [r7, #4] 8001c72: 63bb str r3, [r7, #56] @ 0x38 uint8_t *tempbuff = pData; 8001c74: 68bb ldr r3, [r7, #8] 8001c76: 637b str r3, [r7, #52] @ 0x34 if(NULL == pData) 8001c78: 68bb ldr r3, [r7, #8] 8001c7a: 2b00 cmp r3, #0 8001c7c: d107 bne.n 8001c8e { hsd->ErrorCode |= HAL_SD_ERROR_PARAM; 8001c7e: 68fb ldr r3, [r7, #12] 8001c80: 6b9b ldr r3, [r3, #56] @ 0x38 8001c82: f043 6200 orr.w r2, r3, #134217728 @ 0x8000000 8001c86: 68fb ldr r3, [r7, #12] 8001c88: 639a str r2, [r3, #56] @ 0x38 return HAL_ERROR; 8001c8a: 2301 movs r3, #1 8001c8c: e1c5 b.n 800201a } if(hsd->State == HAL_SD_STATE_READY) 8001c8e: 68fb ldr r3, [r7, #12] 8001c90: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 8001c94: b2db uxtb r3, r3 8001c96: 2b01 cmp r3, #1 8001c98: f040 81b8 bne.w 800200c { hsd->ErrorCode = HAL_SD_ERROR_NONE; 8001c9c: 68fb ldr r3, [r7, #12] 8001c9e: 2200 movs r2, #0 8001ca0: 639a str r2, [r3, #56] @ 0x38 if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) 8001ca2: 6bba ldr r2, [r7, #56] @ 0x38 8001ca4: 683b ldr r3, [r7, #0] 8001ca6: 441a add r2, r3 8001ca8: 68fb ldr r3, [r7, #12] 8001caa: 6ddb ldr r3, [r3, #92] @ 0x5c 8001cac: 429a cmp r2, r3 8001cae: d907 bls.n 8001cc0 { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; 8001cb0: 68fb ldr r3, [r7, #12] 8001cb2: 6b9b ldr r3, [r3, #56] @ 0x38 8001cb4: f043 7200 orr.w r2, r3, #33554432 @ 0x2000000 8001cb8: 68fb ldr r3, [r7, #12] 8001cba: 639a str r2, [r3, #56] @ 0x38 return HAL_ERROR; 8001cbc: 2301 movs r3, #1 8001cbe: e1ac b.n 800201a } hsd->State = HAL_SD_STATE_BUSY; 8001cc0: 68fb ldr r3, [r7, #12] 8001cc2: 2203 movs r2, #3 8001cc4: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Initialize data control register */ hsd->Instance->DCTRL = 0U; 8001cc8: 68fb ldr r3, [r7, #12] 8001cca: 681b ldr r3, [r3, #0] 8001ccc: 2200 movs r2, #0 8001cce: 62da str r2, [r3, #44] @ 0x2c if(hsd->SdCard.CardType != CARD_SDHC_SDXC) 8001cd0: 68fb ldr r3, [r7, #12] 8001cd2: 6c5b ldr r3, [r3, #68] @ 0x44 8001cd4: 2b01 cmp r3, #1 8001cd6: d002 beq.n 8001cde { add *= 512U; 8001cd8: 6bbb ldr r3, [r7, #56] @ 0x38 8001cda: 025b lsls r3, r3, #9 8001cdc: 63bb str r3, [r7, #56] @ 0x38 } /* Configure the SD DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; 8001cde: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8001ce2: 617b str r3, [r7, #20] config.DataLength = NumberOfBlocks * BLOCKSIZE; 8001ce4: 683b ldr r3, [r7, #0] 8001ce6: 025b lsls r3, r3, #9 8001ce8: 61bb str r3, [r7, #24] config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; 8001cea: 2390 movs r3, #144 @ 0x90 8001cec: 61fb str r3, [r7, #28] config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; 8001cee: 2302 movs r3, #2 8001cf0: 623b str r3, [r7, #32] config.TransferMode = SDIO_TRANSFER_MODE_BLOCK; 8001cf2: 2300 movs r3, #0 8001cf4: 627b str r3, [r7, #36] @ 0x24 config.DPSM = SDIO_DPSM_ENABLE; 8001cf6: 2301 movs r3, #1 8001cf8: 62bb str r3, [r7, #40] @ 0x28 (void)SDIO_ConfigData(hsd->Instance, &config); 8001cfa: 68fb ldr r3, [r7, #12] 8001cfc: 681b ldr r3, [r3, #0] 8001cfe: f107 0214 add.w r2, r7, #20 8001d02: 4611 mov r1, r2 8001d04: 4618 mov r0, r3 8001d06: f001 fc6a bl 80035de /* Read block(s) in polling mode */ if(NumberOfBlocks > 1U) 8001d0a: 683b ldr r3, [r7, #0] 8001d0c: 2b01 cmp r3, #1 8001d0e: d90a bls.n 8001d26 { hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK; 8001d10: 68fb ldr r3, [r7, #12] 8001d12: 2202 movs r2, #2 8001d14: 631a str r2, [r3, #48] @ 0x30 /* Read Multi Block command */ errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add); 8001d16: 68fb ldr r3, [r7, #12] 8001d18: 681b ldr r3, [r3, #0] 8001d1a: 6bb9 ldr r1, [r7, #56] @ 0x38 8001d1c: 4618 mov r0, r3 8001d1e: f001 fccd bl 80036bc 8001d22: 6478 str r0, [r7, #68] @ 0x44 8001d24: e009 b.n 8001d3a } else { hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK; 8001d26: 68fb ldr r3, [r7, #12] 8001d28: 2201 movs r2, #1 8001d2a: 631a str r2, [r3, #48] @ 0x30 /* Read Single Block command */ errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add); 8001d2c: 68fb ldr r3, [r7, #12] 8001d2e: 681b ldr r3, [r3, #0] 8001d30: 6bb9 ldr r1, [r7, #56] @ 0x38 8001d32: 4618 mov r0, r3 8001d34: f001 fca0 bl 8003678 8001d38: 6478 str r0, [r7, #68] @ 0x44 } if(errorstate != HAL_SD_ERROR_NONE) 8001d3a: 6c7b ldr r3, [r7, #68] @ 0x44 8001d3c: 2b00 cmp r3, #0 8001d3e: d012 beq.n 8001d66 { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); 8001d40: 68fb ldr r3, [r7, #12] 8001d42: 681b ldr r3, [r3, #0] 8001d44: 4a7e ldr r2, [pc, #504] @ (8001f40 ) 8001d46: 639a str r2, [r3, #56] @ 0x38 hsd->ErrorCode |= errorstate; 8001d48: 68fb ldr r3, [r7, #12] 8001d4a: 6b9a ldr r2, [r3, #56] @ 0x38 8001d4c: 6c7b ldr r3, [r7, #68] @ 0x44 8001d4e: 431a orrs r2, r3 8001d50: 68fb ldr r3, [r7, #12] 8001d52: 639a str r2, [r3, #56] @ 0x38 hsd->State = HAL_SD_STATE_READY; 8001d54: 68fb ldr r3, [r7, #12] 8001d56: 2201 movs r2, #1 8001d58: f883 2034 strb.w r2, [r3, #52] @ 0x34 hsd->Context = SD_CONTEXT_NONE; 8001d5c: 68fb ldr r3, [r7, #12] 8001d5e: 2200 movs r2, #0 8001d60: 631a str r2, [r3, #48] @ 0x30 return HAL_ERROR; 8001d62: 2301 movs r3, #1 8001d64: e159 b.n 800201a } /* Poll on SDIO flags */ dataremaining = config.DataLength; 8001d66: 69bb ldr r3, [r7, #24] 8001d68: 63fb str r3, [r7, #60] @ 0x3c while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR)) 8001d6a: e061 b.n 8001e30 { if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF) && (dataremaining > 0U)) 8001d6c: 68fb ldr r3, [r7, #12] 8001d6e: 681b ldr r3, [r3, #0] 8001d70: 6b5b ldr r3, [r3, #52] @ 0x34 8001d72: f403 4300 and.w r3, r3, #32768 @ 0x8000 8001d76: 2b00 cmp r3, #0 8001d78: d03c beq.n 8001df4 8001d7a: 6bfb ldr r3, [r7, #60] @ 0x3c 8001d7c: 2b00 cmp r3, #0 8001d7e: d039 beq.n 8001df4 { /* Read data from SDIO Rx FIFO */ for(count = 0U; count < 8U; count++) 8001d80: 2300 movs r3, #0 8001d82: 643b str r3, [r7, #64] @ 0x40 8001d84: e033 b.n 8001dee { data = SDIO_ReadFIFO(hsd->Instance); 8001d86: 68fb ldr r3, [r7, #12] 8001d88: 681b ldr r3, [r3, #0] 8001d8a: 4618 mov r0, r3 8001d8c: f001 fbaa bl 80034e4 8001d90: 62f8 str r0, [r7, #44] @ 0x2c *tempbuff = (uint8_t)(data & 0xFFU); 8001d92: 6afb ldr r3, [r7, #44] @ 0x2c 8001d94: b2da uxtb r2, r3 8001d96: 6b7b ldr r3, [r7, #52] @ 0x34 8001d98: 701a strb r2, [r3, #0] tempbuff++; 8001d9a: 6b7b ldr r3, [r7, #52] @ 0x34 8001d9c: 3301 adds r3, #1 8001d9e: 637b str r3, [r7, #52] @ 0x34 dataremaining--; 8001da0: 6bfb ldr r3, [r7, #60] @ 0x3c 8001da2: 3b01 subs r3, #1 8001da4: 63fb str r3, [r7, #60] @ 0x3c *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); 8001da6: 6afb ldr r3, [r7, #44] @ 0x2c 8001da8: 0a1b lsrs r3, r3, #8 8001daa: b2da uxtb r2, r3 8001dac: 6b7b ldr r3, [r7, #52] @ 0x34 8001dae: 701a strb r2, [r3, #0] tempbuff++; 8001db0: 6b7b ldr r3, [r7, #52] @ 0x34 8001db2: 3301 adds r3, #1 8001db4: 637b str r3, [r7, #52] @ 0x34 dataremaining--; 8001db6: 6bfb ldr r3, [r7, #60] @ 0x3c 8001db8: 3b01 subs r3, #1 8001dba: 63fb str r3, [r7, #60] @ 0x3c *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); 8001dbc: 6afb ldr r3, [r7, #44] @ 0x2c 8001dbe: 0c1b lsrs r3, r3, #16 8001dc0: b2da uxtb r2, r3 8001dc2: 6b7b ldr r3, [r7, #52] @ 0x34 8001dc4: 701a strb r2, [r3, #0] tempbuff++; 8001dc6: 6b7b ldr r3, [r7, #52] @ 0x34 8001dc8: 3301 adds r3, #1 8001dca: 637b str r3, [r7, #52] @ 0x34 dataremaining--; 8001dcc: 6bfb ldr r3, [r7, #60] @ 0x3c 8001dce: 3b01 subs r3, #1 8001dd0: 63fb str r3, [r7, #60] @ 0x3c *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); 8001dd2: 6afb ldr r3, [r7, #44] @ 0x2c 8001dd4: 0e1b lsrs r3, r3, #24 8001dd6: b2da uxtb r2, r3 8001dd8: 6b7b ldr r3, [r7, #52] @ 0x34 8001dda: 701a strb r2, [r3, #0] tempbuff++; 8001ddc: 6b7b ldr r3, [r7, #52] @ 0x34 8001dde: 3301 adds r3, #1 8001de0: 637b str r3, [r7, #52] @ 0x34 dataremaining--; 8001de2: 6bfb ldr r3, [r7, #60] @ 0x3c 8001de4: 3b01 subs r3, #1 8001de6: 63fb str r3, [r7, #60] @ 0x3c for(count = 0U; count < 8U; count++) 8001de8: 6c3b ldr r3, [r7, #64] @ 0x40 8001dea: 3301 adds r3, #1 8001dec: 643b str r3, [r7, #64] @ 0x40 8001dee: 6c3b ldr r3, [r7, #64] @ 0x40 8001df0: 2b07 cmp r3, #7 8001df2: d9c8 bls.n 8001d86 } } if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) 8001df4: f7fe fe02 bl 80009fc 8001df8: 4602 mov r2, r0 8001dfa: 6b3b ldr r3, [r7, #48] @ 0x30 8001dfc: 1ad3 subs r3, r2, r3 8001dfe: 6d3a ldr r2, [r7, #80] @ 0x50 8001e00: 429a cmp r2, r3 8001e02: d902 bls.n 8001e0a 8001e04: 6d3b ldr r3, [r7, #80] @ 0x50 8001e06: 2b00 cmp r3, #0 8001e08: d112 bne.n 8001e30 { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); 8001e0a: 68fb ldr r3, [r7, #12] 8001e0c: 681b ldr r3, [r3, #0] 8001e0e: 4a4c ldr r2, [pc, #304] @ (8001f40 ) 8001e10: 639a str r2, [r3, #56] @ 0x38 hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT; 8001e12: 68fb ldr r3, [r7, #12] 8001e14: 6b9b ldr r3, [r3, #56] @ 0x38 8001e16: f043 4200 orr.w r2, r3, #2147483648 @ 0x80000000 8001e1a: 68fb ldr r3, [r7, #12] 8001e1c: 639a str r2, [r3, #56] @ 0x38 hsd->State= HAL_SD_STATE_READY; 8001e1e: 68fb ldr r3, [r7, #12] 8001e20: 2201 movs r2, #1 8001e22: f883 2034 strb.w r2, [r3, #52] @ 0x34 hsd->Context = SD_CONTEXT_NONE; 8001e26: 68fb ldr r3, [r7, #12] 8001e28: 2200 movs r2, #0 8001e2a: 631a str r2, [r3, #48] @ 0x30 return HAL_TIMEOUT; 8001e2c: 2303 movs r3, #3 8001e2e: e0f4 b.n 800201a while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR)) 8001e30: 68fb ldr r3, [r7, #12] 8001e32: 681b ldr r3, [r3, #0] 8001e34: 6b5a ldr r2, [r3, #52] @ 0x34 8001e36: f240 332a movw r3, #810 @ 0x32a 8001e3a: 4013 ands r3, r2 8001e3c: 2b00 cmp r3, #0 8001e3e: d095 beq.n 8001d6c } } /* Send stop transmission command in case of multiblock read */ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U)) 8001e40: 68fb ldr r3, [r7, #12] 8001e42: 681b ldr r3, [r3, #0] 8001e44: 6b5b ldr r3, [r3, #52] @ 0x34 8001e46: f403 7380 and.w r3, r3, #256 @ 0x100 8001e4a: 2b00 cmp r3, #0 8001e4c: d022 beq.n 8001e94 8001e4e: 683b ldr r3, [r7, #0] 8001e50: 2b01 cmp r3, #1 8001e52: d91f bls.n 8001e94 { if(hsd->SdCard.CardType != CARD_SECURED) 8001e54: 68fb ldr r3, [r7, #12] 8001e56: 6c5b ldr r3, [r3, #68] @ 0x44 8001e58: 2b03 cmp r3, #3 8001e5a: d01b beq.n 8001e94 { /* Send stop transmission command */ errorstate = SDMMC_CmdStopTransfer(hsd->Instance); 8001e5c: 68fb ldr r3, [r7, #12] 8001e5e: 681b ldr r3, [r3, #0] 8001e60: 4618 mov r0, r3 8001e62: f001 fc91 bl 8003788 8001e66: 6478 str r0, [r7, #68] @ 0x44 if(errorstate != HAL_SD_ERROR_NONE) 8001e68: 6c7b ldr r3, [r7, #68] @ 0x44 8001e6a: 2b00 cmp r3, #0 8001e6c: d012 beq.n 8001e94 { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); 8001e6e: 68fb ldr r3, [r7, #12] 8001e70: 681b ldr r3, [r3, #0] 8001e72: 4a33 ldr r2, [pc, #204] @ (8001f40 ) 8001e74: 639a str r2, [r3, #56] @ 0x38 hsd->ErrorCode |= errorstate; 8001e76: 68fb ldr r3, [r7, #12] 8001e78: 6b9a ldr r2, [r3, #56] @ 0x38 8001e7a: 6c7b ldr r3, [r7, #68] @ 0x44 8001e7c: 431a orrs r2, r3 8001e7e: 68fb ldr r3, [r7, #12] 8001e80: 639a str r2, [r3, #56] @ 0x38 hsd->State = HAL_SD_STATE_READY; 8001e82: 68fb ldr r3, [r7, #12] 8001e84: 2201 movs r2, #1 8001e86: f883 2034 strb.w r2, [r3, #52] @ 0x34 hsd->Context = SD_CONTEXT_NONE; 8001e8a: 68fb ldr r3, [r7, #12] 8001e8c: 2200 movs r2, #0 8001e8e: 631a str r2, [r3, #48] @ 0x30 return HAL_ERROR; 8001e90: 2301 movs r3, #1 8001e92: e0c2 b.n 800201a } } } /* Get error state */ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) || (__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR))) 8001e94: 68fb ldr r3, [r7, #12] 8001e96: 681b ldr r3, [r3, #0] 8001e98: 6b5b ldr r3, [r3, #52] @ 0x34 8001e9a: f003 0308 and.w r3, r3, #8 8001e9e: 2b00 cmp r3, #0 8001ea0: d106 bne.n 8001eb0 8001ea2: 68fb ldr r3, [r7, #12] 8001ea4: 681b ldr r3, [r3, #0] 8001ea6: 6b5b ldr r3, [r3, #52] @ 0x34 8001ea8: f403 7300 and.w r3, r3, #512 @ 0x200 8001eac: 2b00 cmp r3, #0 8001eae: d012 beq.n 8001ed6 { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); 8001eb0: 68fb ldr r3, [r7, #12] 8001eb2: 681b ldr r3, [r3, #0] 8001eb4: 4a22 ldr r2, [pc, #136] @ (8001f40 ) 8001eb6: 639a str r2, [r3, #56] @ 0x38 hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; 8001eb8: 68fb ldr r3, [r7, #12] 8001eba: 6b9b ldr r3, [r3, #56] @ 0x38 8001ebc: f043 0208 orr.w r2, r3, #8 8001ec0: 68fb ldr r3, [r7, #12] 8001ec2: 639a str r2, [r3, #56] @ 0x38 hsd->State = HAL_SD_STATE_READY; 8001ec4: 68fb ldr r3, [r7, #12] 8001ec6: 2201 movs r2, #1 8001ec8: f883 2034 strb.w r2, [r3, #52] @ 0x34 hsd->Context = SD_CONTEXT_NONE; 8001ecc: 68fb ldr r3, [r7, #12] 8001ece: 2200 movs r2, #0 8001ed0: 631a str r2, [r3, #48] @ 0x30 return HAL_ERROR; 8001ed2: 2301 movs r3, #1 8001ed4: e0a1 b.n 800201a } else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL)) 8001ed6: 68fb ldr r3, [r7, #12] 8001ed8: 681b ldr r3, [r3, #0] 8001eda: 6b5b ldr r3, [r3, #52] @ 0x34 8001edc: f003 0302 and.w r3, r3, #2 8001ee0: 2b00 cmp r3, #0 8001ee2: d012 beq.n 8001f0a { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); 8001ee4: 68fb ldr r3, [r7, #12] 8001ee6: 681b ldr r3, [r3, #0] 8001ee8: 4a15 ldr r2, [pc, #84] @ (8001f40 ) 8001eea: 639a str r2, [r3, #56] @ 0x38 hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; 8001eec: 68fb ldr r3, [r7, #12] 8001eee: 6b9b ldr r3, [r3, #56] @ 0x38 8001ef0: f043 0202 orr.w r2, r3, #2 8001ef4: 68fb ldr r3, [r7, #12] 8001ef6: 639a str r2, [r3, #56] @ 0x38 hsd->State = HAL_SD_STATE_READY; 8001ef8: 68fb ldr r3, [r7, #12] 8001efa: 2201 movs r2, #1 8001efc: f883 2034 strb.w r2, [r3, #52] @ 0x34 hsd->Context = SD_CONTEXT_NONE; 8001f00: 68fb ldr r3, [r7, #12] 8001f02: 2200 movs r2, #0 8001f04: 631a str r2, [r3, #48] @ 0x30 return HAL_ERROR; 8001f06: 2301 movs r3, #1 8001f08: e087 b.n 800201a } else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR)) 8001f0a: 68fb ldr r3, [r7, #12] 8001f0c: 681b ldr r3, [r3, #0] 8001f0e: 6b5b ldr r3, [r3, #52] @ 0x34 8001f10: f003 0320 and.w r3, r3, #32 8001f14: 2b00 cmp r3, #0 8001f16: d064 beq.n 8001fe2 { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); 8001f18: 68fb ldr r3, [r7, #12] 8001f1a: 681b ldr r3, [r3, #0] 8001f1c: 4a08 ldr r2, [pc, #32] @ (8001f40 ) 8001f1e: 639a str r2, [r3, #56] @ 0x38 hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN; 8001f20: 68fb ldr r3, [r7, #12] 8001f22: 6b9b ldr r3, [r3, #56] @ 0x38 8001f24: f043 0220 orr.w r2, r3, #32 8001f28: 68fb ldr r3, [r7, #12] 8001f2a: 639a str r2, [r3, #56] @ 0x38 hsd->State = HAL_SD_STATE_READY; 8001f2c: 68fb ldr r3, [r7, #12] 8001f2e: 2201 movs r2, #1 8001f30: f883 2034 strb.w r2, [r3, #52] @ 0x34 hsd->Context = SD_CONTEXT_NONE; 8001f34: 68fb ldr r3, [r7, #12] 8001f36: 2200 movs r2, #0 8001f38: 631a str r2, [r3, #48] @ 0x30 return HAL_ERROR; 8001f3a: 2301 movs r3, #1 8001f3c: e06d b.n 800201a 8001f3e: bf00 nop 8001f40: 004005ff .word 0x004005ff } /* Empty FIFO if there is still any data */ while ((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (dataremaining > 0U)) { data = SDIO_ReadFIFO(hsd->Instance); 8001f44: 68fb ldr r3, [r7, #12] 8001f46: 681b ldr r3, [r3, #0] 8001f48: 4618 mov r0, r3 8001f4a: f001 facb bl 80034e4 8001f4e: 62f8 str r0, [r7, #44] @ 0x2c *tempbuff = (uint8_t)(data & 0xFFU); 8001f50: 6afb ldr r3, [r7, #44] @ 0x2c 8001f52: b2da uxtb r2, r3 8001f54: 6b7b ldr r3, [r7, #52] @ 0x34 8001f56: 701a strb r2, [r3, #0] tempbuff++; 8001f58: 6b7b ldr r3, [r7, #52] @ 0x34 8001f5a: 3301 adds r3, #1 8001f5c: 637b str r3, [r7, #52] @ 0x34 dataremaining--; 8001f5e: 6bfb ldr r3, [r7, #60] @ 0x3c 8001f60: 3b01 subs r3, #1 8001f62: 63fb str r3, [r7, #60] @ 0x3c *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); 8001f64: 6afb ldr r3, [r7, #44] @ 0x2c 8001f66: 0a1b lsrs r3, r3, #8 8001f68: b2da uxtb r2, r3 8001f6a: 6b7b ldr r3, [r7, #52] @ 0x34 8001f6c: 701a strb r2, [r3, #0] tempbuff++; 8001f6e: 6b7b ldr r3, [r7, #52] @ 0x34 8001f70: 3301 adds r3, #1 8001f72: 637b str r3, [r7, #52] @ 0x34 dataremaining--; 8001f74: 6bfb ldr r3, [r7, #60] @ 0x3c 8001f76: 3b01 subs r3, #1 8001f78: 63fb str r3, [r7, #60] @ 0x3c *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); 8001f7a: 6afb ldr r3, [r7, #44] @ 0x2c 8001f7c: 0c1b lsrs r3, r3, #16 8001f7e: b2da uxtb r2, r3 8001f80: 6b7b ldr r3, [r7, #52] @ 0x34 8001f82: 701a strb r2, [r3, #0] tempbuff++; 8001f84: 6b7b ldr r3, [r7, #52] @ 0x34 8001f86: 3301 adds r3, #1 8001f88: 637b str r3, [r7, #52] @ 0x34 dataremaining--; 8001f8a: 6bfb ldr r3, [r7, #60] @ 0x3c 8001f8c: 3b01 subs r3, #1 8001f8e: 63fb str r3, [r7, #60] @ 0x3c *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); 8001f90: 6afb ldr r3, [r7, #44] @ 0x2c 8001f92: 0e1b lsrs r3, r3, #24 8001f94: b2da uxtb r2, r3 8001f96: 6b7b ldr r3, [r7, #52] @ 0x34 8001f98: 701a strb r2, [r3, #0] tempbuff++; 8001f9a: 6b7b ldr r3, [r7, #52] @ 0x34 8001f9c: 3301 adds r3, #1 8001f9e: 637b str r3, [r7, #52] @ 0x34 dataremaining--; 8001fa0: 6bfb ldr r3, [r7, #60] @ 0x3c 8001fa2: 3b01 subs r3, #1 8001fa4: 63fb str r3, [r7, #60] @ 0x3c if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) 8001fa6: f7fe fd29 bl 80009fc 8001faa: 4602 mov r2, r0 8001fac: 6b3b ldr r3, [r7, #48] @ 0x30 8001fae: 1ad3 subs r3, r2, r3 8001fb0: 6d3a ldr r2, [r7, #80] @ 0x50 8001fb2: 429a cmp r2, r3 8001fb4: d902 bls.n 8001fbc 8001fb6: 6d3b ldr r3, [r7, #80] @ 0x50 8001fb8: 2b00 cmp r3, #0 8001fba: d112 bne.n 8001fe2 { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); 8001fbc: 68fb ldr r3, [r7, #12] 8001fbe: 681b ldr r3, [r3, #0] 8001fc0: 4a18 ldr r2, [pc, #96] @ (8002024 ) 8001fc2: 639a str r2, [r3, #56] @ 0x38 hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT; 8001fc4: 68fb ldr r3, [r7, #12] 8001fc6: 6b9b ldr r3, [r3, #56] @ 0x38 8001fc8: f043 4200 orr.w r2, r3, #2147483648 @ 0x80000000 8001fcc: 68fb ldr r3, [r7, #12] 8001fce: 639a str r2, [r3, #56] @ 0x38 hsd->State= HAL_SD_STATE_READY; 8001fd0: 68fb ldr r3, [r7, #12] 8001fd2: 2201 movs r2, #1 8001fd4: f883 2034 strb.w r2, [r3, #52] @ 0x34 hsd->Context = SD_CONTEXT_NONE; 8001fd8: 68fb ldr r3, [r7, #12] 8001fda: 2200 movs r2, #0 8001fdc: 631a str r2, [r3, #48] @ 0x30 return HAL_ERROR; 8001fde: 2301 movs r3, #1 8001fe0: e01b b.n 800201a while ((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (dataremaining > 0U)) 8001fe2: 68fb ldr r3, [r7, #12] 8001fe4: 681b ldr r3, [r3, #0] 8001fe6: 6b5b ldr r3, [r3, #52] @ 0x34 8001fe8: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8001fec: 2b00 cmp r3, #0 8001fee: d002 beq.n 8001ff6 8001ff0: 6bfb ldr r3, [r7, #60] @ 0x3c 8001ff2: 2b00 cmp r3, #0 8001ff4: d1a6 bne.n 8001f44 } } /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS); 8001ff6: 68fb ldr r3, [r7, #12] 8001ff8: 681b ldr r3, [r3, #0] 8001ffa: f240 523a movw r2, #1338 @ 0x53a 8001ffe: 639a str r2, [r3, #56] @ 0x38 hsd->State = HAL_SD_STATE_READY; 8002000: 68fb ldr r3, [r7, #12] 8002002: 2201 movs r2, #1 8002004: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_OK; 8002008: 2300 movs r3, #0 800200a: e006 b.n 800201a } else { hsd->ErrorCode |= HAL_SD_ERROR_BUSY; 800200c: 68fb ldr r3, [r7, #12] 800200e: 6b9b ldr r3, [r3, #56] @ 0x38 8002010: f043 5200 orr.w r2, r3, #536870912 @ 0x20000000 8002014: 68fb ldr r3, [r7, #12] 8002016: 639a str r2, [r3, #56] @ 0x38 return HAL_ERROR; 8002018: 2301 movs r3, #1 } } 800201a: 4618 mov r0, r3 800201c: 3748 adds r7, #72 @ 0x48 800201e: 46bd mov sp, r7 8002020: bd80 pop {r7, pc} 8002022: bf00 nop 8002024: 004005ff .word 0x004005ff 08002028 : * @param NumberOfBlocks: Number of SD blocks to write * @param Timeout: Specify timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) { 8002028: b580 push {r7, lr} 800202a: b092 sub sp, #72 @ 0x48 800202c: af00 add r7, sp, #0 800202e: 60f8 str r0, [r7, #12] 8002030: 60b9 str r1, [r7, #8] 8002032: 607a str r2, [r7, #4] 8002034: 603b str r3, [r7, #0] SDIO_DataInitTypeDef config; uint32_t errorstate; uint32_t tickstart = HAL_GetTick(); 8002036: f7fe fce1 bl 80009fc 800203a: 6338 str r0, [r7, #48] @ 0x30 uint32_t count, data, dataremaining; uint32_t add = BlockAdd; 800203c: 687b ldr r3, [r7, #4] 800203e: 63bb str r3, [r7, #56] @ 0x38 uint8_t *tempbuff = pData; 8002040: 68bb ldr r3, [r7, #8] 8002042: 637b str r3, [r7, #52] @ 0x34 if(NULL == pData) 8002044: 68bb ldr r3, [r7, #8] 8002046: 2b00 cmp r3, #0 8002048: d107 bne.n 800205a { hsd->ErrorCode |= HAL_SD_ERROR_PARAM; 800204a: 68fb ldr r3, [r7, #12] 800204c: 6b9b ldr r3, [r3, #56] @ 0x38 800204e: f043 6200 orr.w r2, r3, #134217728 @ 0x8000000 8002052: 68fb ldr r3, [r7, #12] 8002054: 639a str r2, [r3, #56] @ 0x38 return HAL_ERROR; 8002056: 2301 movs r3, #1 8002058: e16d b.n 8002336 } if(hsd->State == HAL_SD_STATE_READY) 800205a: 68fb ldr r3, [r7, #12] 800205c: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 8002060: b2db uxtb r3, r3 8002062: 2b01 cmp r3, #1 8002064: f040 8160 bne.w 8002328 { hsd->ErrorCode = HAL_SD_ERROR_NONE; 8002068: 68fb ldr r3, [r7, #12] 800206a: 2200 movs r2, #0 800206c: 639a str r2, [r3, #56] @ 0x38 if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) 800206e: 6bba ldr r2, [r7, #56] @ 0x38 8002070: 683b ldr r3, [r7, #0] 8002072: 441a add r2, r3 8002074: 68fb ldr r3, [r7, #12] 8002076: 6ddb ldr r3, [r3, #92] @ 0x5c 8002078: 429a cmp r2, r3 800207a: d907 bls.n 800208c { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; 800207c: 68fb ldr r3, [r7, #12] 800207e: 6b9b ldr r3, [r3, #56] @ 0x38 8002080: f043 7200 orr.w r2, r3, #33554432 @ 0x2000000 8002084: 68fb ldr r3, [r7, #12] 8002086: 639a str r2, [r3, #56] @ 0x38 return HAL_ERROR; 8002088: 2301 movs r3, #1 800208a: e154 b.n 8002336 } hsd->State = HAL_SD_STATE_BUSY; 800208c: 68fb ldr r3, [r7, #12] 800208e: 2203 movs r2, #3 8002090: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Initialize data control register */ hsd->Instance->DCTRL = 0U; 8002094: 68fb ldr r3, [r7, #12] 8002096: 681b ldr r3, [r3, #0] 8002098: 2200 movs r2, #0 800209a: 62da str r2, [r3, #44] @ 0x2c if(hsd->SdCard.CardType != CARD_SDHC_SDXC) 800209c: 68fb ldr r3, [r7, #12] 800209e: 6c5b ldr r3, [r3, #68] @ 0x44 80020a0: 2b01 cmp r3, #1 80020a2: d002 beq.n 80020aa { add *= 512U; 80020a4: 6bbb ldr r3, [r7, #56] @ 0x38 80020a6: 025b lsls r3, r3, #9 80020a8: 63bb str r3, [r7, #56] @ 0x38 } /* Configure the SD DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; 80020aa: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80020ae: 61bb str r3, [r7, #24] config.DataLength = NumberOfBlocks * BLOCKSIZE; 80020b0: 683b ldr r3, [r7, #0] 80020b2: 025b lsls r3, r3, #9 80020b4: 61fb str r3, [r7, #28] config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; 80020b6: 2390 movs r3, #144 @ 0x90 80020b8: 623b str r3, [r7, #32] config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD; 80020ba: 2300 movs r3, #0 80020bc: 627b str r3, [r7, #36] @ 0x24 config.TransferMode = SDIO_TRANSFER_MODE_BLOCK; 80020be: 2300 movs r3, #0 80020c0: 62bb str r3, [r7, #40] @ 0x28 config.DPSM = SDIO_DPSM_ENABLE; 80020c2: 2301 movs r3, #1 80020c4: 62fb str r3, [r7, #44] @ 0x2c (void)SDIO_ConfigData(hsd->Instance, &config); 80020c6: 68fb ldr r3, [r7, #12] 80020c8: 681b ldr r3, [r3, #0] 80020ca: f107 0218 add.w r2, r7, #24 80020ce: 4611 mov r1, r2 80020d0: 4618 mov r0, r3 80020d2: f001 fa84 bl 80035de /* Write Blocks in Polling mode */ if(NumberOfBlocks > 1U) 80020d6: 683b ldr r3, [r7, #0] 80020d8: 2b01 cmp r3, #1 80020da: d90a bls.n 80020f2 { hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK; 80020dc: 68fb ldr r3, [r7, #12] 80020de: 2220 movs r2, #32 80020e0: 631a str r2, [r3, #48] @ 0x30 /* Write Multi Block command */ errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add); 80020e2: 68fb ldr r3, [r7, #12] 80020e4: 681b ldr r3, [r3, #0] 80020e6: 6bb9 ldr r1, [r7, #56] @ 0x38 80020e8: 4618 mov r0, r3 80020ea: f001 fb2b bl 8003744 80020ee: 6478 str r0, [r7, #68] @ 0x44 80020f0: e009 b.n 8002106 } else { hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK; 80020f2: 68fb ldr r3, [r7, #12] 80020f4: 2210 movs r2, #16 80020f6: 631a str r2, [r3, #48] @ 0x30 /* Write Single Block command */ errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add); 80020f8: 68fb ldr r3, [r7, #12] 80020fa: 681b ldr r3, [r3, #0] 80020fc: 6bb9 ldr r1, [r7, #56] @ 0x38 80020fe: 4618 mov r0, r3 8002100: f001 fafe bl 8003700 8002104: 6478 str r0, [r7, #68] @ 0x44 } if(errorstate != HAL_SD_ERROR_NONE) 8002106: 6c7b ldr r3, [r7, #68] @ 0x44 8002108: 2b00 cmp r3, #0 800210a: d012 beq.n 8002132 { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); 800210c: 68fb ldr r3, [r7, #12] 800210e: 681b ldr r3, [r3, #0] 8002110: 4a8b ldr r2, [pc, #556] @ (8002340 ) 8002112: 639a str r2, [r3, #56] @ 0x38 hsd->ErrorCode |= errorstate; 8002114: 68fb ldr r3, [r7, #12] 8002116: 6b9a ldr r2, [r3, #56] @ 0x38 8002118: 6c7b ldr r3, [r7, #68] @ 0x44 800211a: 431a orrs r2, r3 800211c: 68fb ldr r3, [r7, #12] 800211e: 639a str r2, [r3, #56] @ 0x38 hsd->State = HAL_SD_STATE_READY; 8002120: 68fb ldr r3, [r7, #12] 8002122: 2201 movs r2, #1 8002124: f883 2034 strb.w r2, [r3, #52] @ 0x34 hsd->Context = SD_CONTEXT_NONE; 8002128: 68fb ldr r3, [r7, #12] 800212a: 2200 movs r2, #0 800212c: 631a str r2, [r3, #48] @ 0x30 return HAL_ERROR; 800212e: 2301 movs r3, #1 8002130: e101 b.n 8002336 } /* Write block(s) in polling mode */ dataremaining = config.DataLength; 8002132: 69fb ldr r3, [r7, #28] 8002134: 63fb str r3, [r7, #60] @ 0x3c while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR)) 8002136: e065 b.n 8002204 { if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE) && (dataremaining > 0U)) 8002138: 68fb ldr r3, [r7, #12] 800213a: 681b ldr r3, [r3, #0] 800213c: 6b5b ldr r3, [r3, #52] @ 0x34 800213e: f403 4380 and.w r3, r3, #16384 @ 0x4000 8002142: 2b00 cmp r3, #0 8002144: d040 beq.n 80021c8 8002146: 6bfb ldr r3, [r7, #60] @ 0x3c 8002148: 2b00 cmp r3, #0 800214a: d03d beq.n 80021c8 { /* Write data to SDIO Tx FIFO */ for(count = 0U; count < 8U; count++) 800214c: 2300 movs r3, #0 800214e: 643b str r3, [r7, #64] @ 0x40 8002150: e037 b.n 80021c2 { data = (uint32_t)(*tempbuff); 8002152: 6b7b ldr r3, [r7, #52] @ 0x34 8002154: 781b ldrb r3, [r3, #0] 8002156: 617b str r3, [r7, #20] tempbuff++; 8002158: 6b7b ldr r3, [r7, #52] @ 0x34 800215a: 3301 adds r3, #1 800215c: 637b str r3, [r7, #52] @ 0x34 dataremaining--; 800215e: 6bfb ldr r3, [r7, #60] @ 0x3c 8002160: 3b01 subs r3, #1 8002162: 63fb str r3, [r7, #60] @ 0x3c data |= ((uint32_t)(*tempbuff) << 8U); 8002164: 6b7b ldr r3, [r7, #52] @ 0x34 8002166: 781b ldrb r3, [r3, #0] 8002168: 021a lsls r2, r3, #8 800216a: 697b ldr r3, [r7, #20] 800216c: 4313 orrs r3, r2 800216e: 617b str r3, [r7, #20] tempbuff++; 8002170: 6b7b ldr r3, [r7, #52] @ 0x34 8002172: 3301 adds r3, #1 8002174: 637b str r3, [r7, #52] @ 0x34 dataremaining--; 8002176: 6bfb ldr r3, [r7, #60] @ 0x3c 8002178: 3b01 subs r3, #1 800217a: 63fb str r3, [r7, #60] @ 0x3c data |= ((uint32_t)(*tempbuff) << 16U); 800217c: 6b7b ldr r3, [r7, #52] @ 0x34 800217e: 781b ldrb r3, [r3, #0] 8002180: 041a lsls r2, r3, #16 8002182: 697b ldr r3, [r7, #20] 8002184: 4313 orrs r3, r2 8002186: 617b str r3, [r7, #20] tempbuff++; 8002188: 6b7b ldr r3, [r7, #52] @ 0x34 800218a: 3301 adds r3, #1 800218c: 637b str r3, [r7, #52] @ 0x34 dataremaining--; 800218e: 6bfb ldr r3, [r7, #60] @ 0x3c 8002190: 3b01 subs r3, #1 8002192: 63fb str r3, [r7, #60] @ 0x3c data |= ((uint32_t)(*tempbuff) << 24U); 8002194: 6b7b ldr r3, [r7, #52] @ 0x34 8002196: 781b ldrb r3, [r3, #0] 8002198: 061a lsls r2, r3, #24 800219a: 697b ldr r3, [r7, #20] 800219c: 4313 orrs r3, r2 800219e: 617b str r3, [r7, #20] tempbuff++; 80021a0: 6b7b ldr r3, [r7, #52] @ 0x34 80021a2: 3301 adds r3, #1 80021a4: 637b str r3, [r7, #52] @ 0x34 dataremaining--; 80021a6: 6bfb ldr r3, [r7, #60] @ 0x3c 80021a8: 3b01 subs r3, #1 80021aa: 63fb str r3, [r7, #60] @ 0x3c (void)SDIO_WriteFIFO(hsd->Instance, &data); 80021ac: 68fb ldr r3, [r7, #12] 80021ae: 681b ldr r3, [r3, #0] 80021b0: f107 0214 add.w r2, r7, #20 80021b4: 4611 mov r1, r2 80021b6: 4618 mov r0, r3 80021b8: f001 f9a0 bl 80034fc for(count = 0U; count < 8U; count++) 80021bc: 6c3b ldr r3, [r7, #64] @ 0x40 80021be: 3301 adds r3, #1 80021c0: 643b str r3, [r7, #64] @ 0x40 80021c2: 6c3b ldr r3, [r7, #64] @ 0x40 80021c4: 2b07 cmp r3, #7 80021c6: d9c4 bls.n 8002152 } } if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) 80021c8: f7fe fc18 bl 80009fc 80021cc: 4602 mov r2, r0 80021ce: 6b3b ldr r3, [r7, #48] @ 0x30 80021d0: 1ad3 subs r3, r2, r3 80021d2: 6d3a ldr r2, [r7, #80] @ 0x50 80021d4: 429a cmp r2, r3 80021d6: d902 bls.n 80021de 80021d8: 6d3b ldr r3, [r7, #80] @ 0x50 80021da: 2b00 cmp r3, #0 80021dc: d112 bne.n 8002204 { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); 80021de: 68fb ldr r3, [r7, #12] 80021e0: 681b ldr r3, [r3, #0] 80021e2: 4a57 ldr r2, [pc, #348] @ (8002340 ) 80021e4: 639a str r2, [r3, #56] @ 0x38 hsd->ErrorCode |= errorstate; 80021e6: 68fb ldr r3, [r7, #12] 80021e8: 6b9a ldr r2, [r3, #56] @ 0x38 80021ea: 6c7b ldr r3, [r7, #68] @ 0x44 80021ec: 431a orrs r2, r3 80021ee: 68fb ldr r3, [r7, #12] 80021f0: 639a str r2, [r3, #56] @ 0x38 hsd->State = HAL_SD_STATE_READY; 80021f2: 68fb ldr r3, [r7, #12] 80021f4: 2201 movs r2, #1 80021f6: f883 2034 strb.w r2, [r3, #52] @ 0x34 hsd->Context = SD_CONTEXT_NONE; 80021fa: 68fb ldr r3, [r7, #12] 80021fc: 2200 movs r2, #0 80021fe: 631a str r2, [r3, #48] @ 0x30 return HAL_TIMEOUT; 8002200: 2303 movs r3, #3 8002202: e098 b.n 8002336 while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR)) 8002204: 68fb ldr r3, [r7, #12] 8002206: 681b ldr r3, [r3, #0] 8002208: 6b5a ldr r2, [r3, #52] @ 0x34 800220a: f240 331a movw r3, #794 @ 0x31a 800220e: 4013 ands r3, r2 8002210: 2b00 cmp r3, #0 8002212: d091 beq.n 8002138 } } /* Send stop transmission command in case of multiblock write */ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U)) 8002214: 68fb ldr r3, [r7, #12] 8002216: 681b ldr r3, [r3, #0] 8002218: 6b5b ldr r3, [r3, #52] @ 0x34 800221a: f403 7380 and.w r3, r3, #256 @ 0x100 800221e: 2b00 cmp r3, #0 8002220: d022 beq.n 8002268 8002222: 683b ldr r3, [r7, #0] 8002224: 2b01 cmp r3, #1 8002226: d91f bls.n 8002268 { if(hsd->SdCard.CardType != CARD_SECURED) 8002228: 68fb ldr r3, [r7, #12] 800222a: 6c5b ldr r3, [r3, #68] @ 0x44 800222c: 2b03 cmp r3, #3 800222e: d01b beq.n 8002268 { /* Send stop transmission command */ errorstate = SDMMC_CmdStopTransfer(hsd->Instance); 8002230: 68fb ldr r3, [r7, #12] 8002232: 681b ldr r3, [r3, #0] 8002234: 4618 mov r0, r3 8002236: f001 faa7 bl 8003788 800223a: 6478 str r0, [r7, #68] @ 0x44 if(errorstate != HAL_SD_ERROR_NONE) 800223c: 6c7b ldr r3, [r7, #68] @ 0x44 800223e: 2b00 cmp r3, #0 8002240: d012 beq.n 8002268 { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); 8002242: 68fb ldr r3, [r7, #12] 8002244: 681b ldr r3, [r3, #0] 8002246: 4a3e ldr r2, [pc, #248] @ (8002340 ) 8002248: 639a str r2, [r3, #56] @ 0x38 hsd->ErrorCode |= errorstate; 800224a: 68fb ldr r3, [r7, #12] 800224c: 6b9a ldr r2, [r3, #56] @ 0x38 800224e: 6c7b ldr r3, [r7, #68] @ 0x44 8002250: 431a orrs r2, r3 8002252: 68fb ldr r3, [r7, #12] 8002254: 639a str r2, [r3, #56] @ 0x38 hsd->State = HAL_SD_STATE_READY; 8002256: 68fb ldr r3, [r7, #12] 8002258: 2201 movs r2, #1 800225a: f883 2034 strb.w r2, [r3, #52] @ 0x34 hsd->Context = SD_CONTEXT_NONE; 800225e: 68fb ldr r3, [r7, #12] 8002260: 2200 movs r2, #0 8002262: 631a str r2, [r3, #48] @ 0x30 return HAL_ERROR; 8002264: 2301 movs r3, #1 8002266: e066 b.n 8002336 } } } /* Get error state */ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) || (__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR))) 8002268: 68fb ldr r3, [r7, #12] 800226a: 681b ldr r3, [r3, #0] 800226c: 6b5b ldr r3, [r3, #52] @ 0x34 800226e: f003 0308 and.w r3, r3, #8 8002272: 2b00 cmp r3, #0 8002274: d106 bne.n 8002284 8002276: 68fb ldr r3, [r7, #12] 8002278: 681b ldr r3, [r3, #0] 800227a: 6b5b ldr r3, [r3, #52] @ 0x34 800227c: f403 7300 and.w r3, r3, #512 @ 0x200 8002280: 2b00 cmp r3, #0 8002282: d012 beq.n 80022aa { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); 8002284: 68fb ldr r3, [r7, #12] 8002286: 681b ldr r3, [r3, #0] 8002288: 4a2d ldr r2, [pc, #180] @ (8002340 ) 800228a: 639a str r2, [r3, #56] @ 0x38 hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; 800228c: 68fb ldr r3, [r7, #12] 800228e: 6b9b ldr r3, [r3, #56] @ 0x38 8002290: f043 0208 orr.w r2, r3, #8 8002294: 68fb ldr r3, [r7, #12] 8002296: 639a str r2, [r3, #56] @ 0x38 hsd->State = HAL_SD_STATE_READY; 8002298: 68fb ldr r3, [r7, #12] 800229a: 2201 movs r2, #1 800229c: f883 2034 strb.w r2, [r3, #52] @ 0x34 hsd->Context = SD_CONTEXT_NONE; 80022a0: 68fb ldr r3, [r7, #12] 80022a2: 2200 movs r2, #0 80022a4: 631a str r2, [r3, #48] @ 0x30 return HAL_ERROR; 80022a6: 2301 movs r3, #1 80022a8: e045 b.n 8002336 } else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL)) 80022aa: 68fb ldr r3, [r7, #12] 80022ac: 681b ldr r3, [r3, #0] 80022ae: 6b5b ldr r3, [r3, #52] @ 0x34 80022b0: f003 0302 and.w r3, r3, #2 80022b4: 2b00 cmp r3, #0 80022b6: d012 beq.n 80022de { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); 80022b8: 68fb ldr r3, [r7, #12] 80022ba: 681b ldr r3, [r3, #0] 80022bc: 4a20 ldr r2, [pc, #128] @ (8002340 ) 80022be: 639a str r2, [r3, #56] @ 0x38 hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; 80022c0: 68fb ldr r3, [r7, #12] 80022c2: 6b9b ldr r3, [r3, #56] @ 0x38 80022c4: f043 0202 orr.w r2, r3, #2 80022c8: 68fb ldr r3, [r7, #12] 80022ca: 639a str r2, [r3, #56] @ 0x38 hsd->State = HAL_SD_STATE_READY; 80022cc: 68fb ldr r3, [r7, #12] 80022ce: 2201 movs r2, #1 80022d0: f883 2034 strb.w r2, [r3, #52] @ 0x34 hsd->Context = SD_CONTEXT_NONE; 80022d4: 68fb ldr r3, [r7, #12] 80022d6: 2200 movs r2, #0 80022d8: 631a str r2, [r3, #48] @ 0x30 return HAL_ERROR; 80022da: 2301 movs r3, #1 80022dc: e02b b.n 8002336 } else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR)) 80022de: 68fb ldr r3, [r7, #12] 80022e0: 681b ldr r3, [r3, #0] 80022e2: 6b5b ldr r3, [r3, #52] @ 0x34 80022e4: f003 0310 and.w r3, r3, #16 80022e8: 2b00 cmp r3, #0 80022ea: d012 beq.n 8002312 { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); 80022ec: 68fb ldr r3, [r7, #12] 80022ee: 681b ldr r3, [r3, #0] 80022f0: 4a13 ldr r2, [pc, #76] @ (8002340 ) 80022f2: 639a str r2, [r3, #56] @ 0x38 hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN; 80022f4: 68fb ldr r3, [r7, #12] 80022f6: 6b9b ldr r3, [r3, #56] @ 0x38 80022f8: f043 0210 orr.w r2, r3, #16 80022fc: 68fb ldr r3, [r7, #12] 80022fe: 639a str r2, [r3, #56] @ 0x38 hsd->State = HAL_SD_STATE_READY; 8002300: 68fb ldr r3, [r7, #12] 8002302: 2201 movs r2, #1 8002304: f883 2034 strb.w r2, [r3, #52] @ 0x34 hsd->Context = SD_CONTEXT_NONE; 8002308: 68fb ldr r3, [r7, #12] 800230a: 2200 movs r2, #0 800230c: 631a str r2, [r3, #48] @ 0x30 return HAL_ERROR; 800230e: 2301 movs r3, #1 8002310: e011 b.n 8002336 { /* Nothing to do */ } /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS); 8002312: 68fb ldr r3, [r7, #12] 8002314: 681b ldr r3, [r3, #0] 8002316: f240 523a movw r2, #1338 @ 0x53a 800231a: 639a str r2, [r3, #56] @ 0x38 hsd->State = HAL_SD_STATE_READY; 800231c: 68fb ldr r3, [r7, #12] 800231e: 2201 movs r2, #1 8002320: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_OK; 8002324: 2300 movs r3, #0 8002326: e006 b.n 8002336 } else { hsd->ErrorCode |= HAL_SD_ERROR_BUSY; 8002328: 68fb ldr r3, [r7, #12] 800232a: 6b9b ldr r3, [r3, #56] @ 0x38 800232c: f043 5200 orr.w r2, r3, #536870912 @ 0x20000000 8002330: 68fb ldr r3, [r7, #12] 8002332: 639a str r2, [r3, #56] @ 0x38 return HAL_ERROR; 8002334: 2301 movs r3, #1 } } 8002336: 4618 mov r0, r3 8002338: 3748 adds r7, #72 @ 0x48 800233a: 46bd mov sp, r7 800233c: bd80 pop {r7, pc} 800233e: bf00 nop 8002340: 004005ff .word 0x004005ff 08002344 : * @param pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that * contains all CSD register parameters * @retval HAL status */ HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD) { 8002344: b480 push {r7} 8002346: b083 sub sp, #12 8002348: af00 add r7, sp, #0 800234a: 6078 str r0, [r7, #4] 800234c: 6039 str r1, [r7, #0] pCSD->CSDStruct = (uint8_t)((hsd->CSD[0] & 0xC0000000U) >> 30U); 800234e: 687b ldr r3, [r7, #4] 8002350: 6e5b ldr r3, [r3, #100] @ 0x64 8002352: 0f9b lsrs r3, r3, #30 8002354: b2da uxtb r2, r3 8002356: 683b ldr r3, [r7, #0] 8002358: 701a strb r2, [r3, #0] pCSD->SysSpecVersion = (uint8_t)((hsd->CSD[0] & 0x3C000000U) >> 26U); 800235a: 687b ldr r3, [r7, #4] 800235c: 6e5b ldr r3, [r3, #100] @ 0x64 800235e: 0e9b lsrs r3, r3, #26 8002360: b2db uxtb r3, r3 8002362: f003 030f and.w r3, r3, #15 8002366: b2da uxtb r2, r3 8002368: 683b ldr r3, [r7, #0] 800236a: 705a strb r2, [r3, #1] pCSD->Reserved1 = (uint8_t)((hsd->CSD[0] & 0x03000000U) >> 24U); 800236c: 687b ldr r3, [r7, #4] 800236e: 6e5b ldr r3, [r3, #100] @ 0x64 8002370: 0e1b lsrs r3, r3, #24 8002372: b2db uxtb r3, r3 8002374: f003 0303 and.w r3, r3, #3 8002378: b2da uxtb r2, r3 800237a: 683b ldr r3, [r7, #0] 800237c: 709a strb r2, [r3, #2] pCSD->TAAC = (uint8_t)((hsd->CSD[0] & 0x00FF0000U) >> 16U); 800237e: 687b ldr r3, [r7, #4] 8002380: 6e5b ldr r3, [r3, #100] @ 0x64 8002382: 0c1b lsrs r3, r3, #16 8002384: b2da uxtb r2, r3 8002386: 683b ldr r3, [r7, #0] 8002388: 70da strb r2, [r3, #3] pCSD->NSAC = (uint8_t)((hsd->CSD[0] & 0x0000FF00U) >> 8U); 800238a: 687b ldr r3, [r7, #4] 800238c: 6e5b ldr r3, [r3, #100] @ 0x64 800238e: 0a1b lsrs r3, r3, #8 8002390: b2da uxtb r2, r3 8002392: 683b ldr r3, [r7, #0] 8002394: 711a strb r2, [r3, #4] pCSD->MaxBusClkFrec = (uint8_t)(hsd->CSD[0] & 0x000000FFU); 8002396: 687b ldr r3, [r7, #4] 8002398: 6e5b ldr r3, [r3, #100] @ 0x64 800239a: b2da uxtb r2, r3 800239c: 683b ldr r3, [r7, #0] 800239e: 715a strb r2, [r3, #5] pCSD->CardComdClasses = (uint16_t)((hsd->CSD[1] & 0xFFF00000U) >> 20U); 80023a0: 687b ldr r3, [r7, #4] 80023a2: 6e9b ldr r3, [r3, #104] @ 0x68 80023a4: 0d1b lsrs r3, r3, #20 80023a6: b29a uxth r2, r3 80023a8: 683b ldr r3, [r7, #0] 80023aa: 80da strh r2, [r3, #6] pCSD->RdBlockLen = (uint8_t)((hsd->CSD[1] & 0x000F0000U) >> 16U); 80023ac: 687b ldr r3, [r7, #4] 80023ae: 6e9b ldr r3, [r3, #104] @ 0x68 80023b0: 0c1b lsrs r3, r3, #16 80023b2: b2db uxtb r3, r3 80023b4: f003 030f and.w r3, r3, #15 80023b8: b2da uxtb r2, r3 80023ba: 683b ldr r3, [r7, #0] 80023bc: 721a strb r2, [r3, #8] pCSD->PartBlockRead = (uint8_t)((hsd->CSD[1] & 0x00008000U) >> 15U); 80023be: 687b ldr r3, [r7, #4] 80023c0: 6e9b ldr r3, [r3, #104] @ 0x68 80023c2: 0bdb lsrs r3, r3, #15 80023c4: b2db uxtb r3, r3 80023c6: f003 0301 and.w r3, r3, #1 80023ca: b2da uxtb r2, r3 80023cc: 683b ldr r3, [r7, #0] 80023ce: 725a strb r2, [r3, #9] pCSD->WrBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00004000U) >> 14U); 80023d0: 687b ldr r3, [r7, #4] 80023d2: 6e9b ldr r3, [r3, #104] @ 0x68 80023d4: 0b9b lsrs r3, r3, #14 80023d6: b2db uxtb r3, r3 80023d8: f003 0301 and.w r3, r3, #1 80023dc: b2da uxtb r2, r3 80023de: 683b ldr r3, [r7, #0] 80023e0: 729a strb r2, [r3, #10] pCSD->RdBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00002000U) >> 13U); 80023e2: 687b ldr r3, [r7, #4] 80023e4: 6e9b ldr r3, [r3, #104] @ 0x68 80023e6: 0b5b lsrs r3, r3, #13 80023e8: b2db uxtb r3, r3 80023ea: f003 0301 and.w r3, r3, #1 80023ee: b2da uxtb r2, r3 80023f0: 683b ldr r3, [r7, #0] 80023f2: 72da strb r2, [r3, #11] pCSD->DSRImpl = (uint8_t)((hsd->CSD[1] & 0x00001000U) >> 12U); 80023f4: 687b ldr r3, [r7, #4] 80023f6: 6e9b ldr r3, [r3, #104] @ 0x68 80023f8: 0b1b lsrs r3, r3, #12 80023fa: b2db uxtb r3, r3 80023fc: f003 0301 and.w r3, r3, #1 8002400: b2da uxtb r2, r3 8002402: 683b ldr r3, [r7, #0] 8002404: 731a strb r2, [r3, #12] pCSD->Reserved2 = 0U; /*!< Reserved */ 8002406: 683b ldr r3, [r7, #0] 8002408: 2200 movs r2, #0 800240a: 735a strb r2, [r3, #13] if(hsd->SdCard.CardType == CARD_SDSC) 800240c: 687b ldr r3, [r7, #4] 800240e: 6c5b ldr r3, [r3, #68] @ 0x44 8002410: 2b00 cmp r3, #0 8002412: d163 bne.n 80024dc { pCSD->DeviceSize = (((hsd->CSD[1] & 0x000003FFU) << 2U) | ((hsd->CSD[2] & 0xC0000000U) >> 30U)); 8002414: 687b ldr r3, [r7, #4] 8002416: 6e9b ldr r3, [r3, #104] @ 0x68 8002418: 009a lsls r2, r3, #2 800241a: f640 73fc movw r3, #4092 @ 0xffc 800241e: 4013 ands r3, r2 8002420: 687a ldr r2, [r7, #4] 8002422: 6ed2 ldr r2, [r2, #108] @ 0x6c 8002424: 0f92 lsrs r2, r2, #30 8002426: 431a orrs r2, r3 8002428: 683b ldr r3, [r7, #0] 800242a: 611a str r2, [r3, #16] pCSD->MaxRdCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x38000000U) >> 27U); 800242c: 687b ldr r3, [r7, #4] 800242e: 6edb ldr r3, [r3, #108] @ 0x6c 8002430: 0edb lsrs r3, r3, #27 8002432: b2db uxtb r3, r3 8002434: f003 0307 and.w r3, r3, #7 8002438: b2da uxtb r2, r3 800243a: 683b ldr r3, [r7, #0] 800243c: 751a strb r2, [r3, #20] pCSD->MaxRdCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x07000000U) >> 24U); 800243e: 687b ldr r3, [r7, #4] 8002440: 6edb ldr r3, [r3, #108] @ 0x6c 8002442: 0e1b lsrs r3, r3, #24 8002444: b2db uxtb r3, r3 8002446: f003 0307 and.w r3, r3, #7 800244a: b2da uxtb r2, r3 800244c: 683b ldr r3, [r7, #0] 800244e: 755a strb r2, [r3, #21] pCSD->MaxWrCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x00E00000U) >> 21U); 8002450: 687b ldr r3, [r7, #4] 8002452: 6edb ldr r3, [r3, #108] @ 0x6c 8002454: 0d5b lsrs r3, r3, #21 8002456: b2db uxtb r3, r3 8002458: f003 0307 and.w r3, r3, #7 800245c: b2da uxtb r2, r3 800245e: 683b ldr r3, [r7, #0] 8002460: 759a strb r2, [r3, #22] pCSD->MaxWrCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x001C0000U) >> 18U); 8002462: 687b ldr r3, [r7, #4] 8002464: 6edb ldr r3, [r3, #108] @ 0x6c 8002466: 0c9b lsrs r3, r3, #18 8002468: b2db uxtb r3, r3 800246a: f003 0307 and.w r3, r3, #7 800246e: b2da uxtb r2, r3 8002470: 683b ldr r3, [r7, #0] 8002472: 75da strb r2, [r3, #23] pCSD->DeviceSizeMul = (uint8_t)((hsd->CSD[2] & 0x00038000U) >> 15U); 8002474: 687b ldr r3, [r7, #4] 8002476: 6edb ldr r3, [r3, #108] @ 0x6c 8002478: 0bdb lsrs r3, r3, #15 800247a: b2db uxtb r3, r3 800247c: f003 0307 and.w r3, r3, #7 8002480: b2da uxtb r2, r3 8002482: 683b ldr r3, [r7, #0] 8002484: 761a strb r2, [r3, #24] hsd->SdCard.BlockNbr = (pCSD->DeviceSize + 1U) ; 8002486: 683b ldr r3, [r7, #0] 8002488: 691b ldr r3, [r3, #16] 800248a: 1c5a adds r2, r3, #1 800248c: 687b ldr r3, [r7, #4] 800248e: 655a str r2, [r3, #84] @ 0x54 hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U)); 8002490: 683b ldr r3, [r7, #0] 8002492: 7e1b ldrb r3, [r3, #24] 8002494: b2db uxtb r3, r3 8002496: f003 0307 and.w r3, r3, #7 800249a: 3302 adds r3, #2 800249c: 2201 movs r2, #1 800249e: fa02 f303 lsl.w r3, r2, r3 80024a2: 687a ldr r2, [r7, #4] 80024a4: 6d52 ldr r2, [r2, #84] @ 0x54 80024a6: fb03 f202 mul.w r2, r3, r2 80024aa: 687b ldr r3, [r7, #4] 80024ac: 655a str r2, [r3, #84] @ 0x54 hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU)); 80024ae: 683b ldr r3, [r7, #0] 80024b0: 7a1b ldrb r3, [r3, #8] 80024b2: b2db uxtb r3, r3 80024b4: f003 030f and.w r3, r3, #15 80024b8: 2201 movs r2, #1 80024ba: 409a lsls r2, r3 80024bc: 687b ldr r3, [r7, #4] 80024be: 659a str r2, [r3, #88] @ 0x58 hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U); 80024c0: 687b ldr r3, [r7, #4] 80024c2: 6d5b ldr r3, [r3, #84] @ 0x54 80024c4: 687a ldr r2, [r7, #4] 80024c6: 6d92 ldr r2, [r2, #88] @ 0x58 80024c8: 0a52 lsrs r2, r2, #9 80024ca: fb03 f202 mul.w r2, r3, r2 80024ce: 687b ldr r3, [r7, #4] 80024d0: 65da str r2, [r3, #92] @ 0x5c hsd->SdCard.LogBlockSize = 512U; 80024d2: 687b ldr r3, [r7, #4] 80024d4: f44f 7200 mov.w r2, #512 @ 0x200 80024d8: 661a str r2, [r3, #96] @ 0x60 80024da: e031 b.n 8002540 } else if(hsd->SdCard.CardType == CARD_SDHC_SDXC) 80024dc: 687b ldr r3, [r7, #4] 80024de: 6c5b ldr r3, [r3, #68] @ 0x44 80024e0: 2b01 cmp r3, #1 80024e2: d11d bne.n 8002520 { /* Byte 7 */ pCSD->DeviceSize = (((hsd->CSD[1] & 0x0000003FU) << 16U) | ((hsd->CSD[2] & 0xFFFF0000U) >> 16U)); 80024e4: 687b ldr r3, [r7, #4] 80024e6: 6e9b ldr r3, [r3, #104] @ 0x68 80024e8: 041b lsls r3, r3, #16 80024ea: f403 127c and.w r2, r3, #4128768 @ 0x3f0000 80024ee: 687b ldr r3, [r7, #4] 80024f0: 6edb ldr r3, [r3, #108] @ 0x6c 80024f2: 0c1b lsrs r3, r3, #16 80024f4: 431a orrs r2, r3 80024f6: 683b ldr r3, [r7, #0] 80024f8: 611a str r2, [r3, #16] hsd->SdCard.BlockNbr = ((pCSD->DeviceSize + 1U) * 1024U); 80024fa: 683b ldr r3, [r7, #0] 80024fc: 691b ldr r3, [r3, #16] 80024fe: 3301 adds r3, #1 8002500: 029a lsls r2, r3, #10 8002502: 687b ldr r3, [r7, #4] 8002504: 655a str r2, [r3, #84] @ 0x54 hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr; 8002506: 687b ldr r3, [r7, #4] 8002508: 6d5a ldr r2, [r3, #84] @ 0x54 800250a: 687b ldr r3, [r7, #4] 800250c: 65da str r2, [r3, #92] @ 0x5c hsd->SdCard.BlockSize = 512U; 800250e: 687b ldr r3, [r7, #4] 8002510: f44f 7200 mov.w r2, #512 @ 0x200 8002514: 659a str r2, [r3, #88] @ 0x58 hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize; 8002516: 687b ldr r3, [r7, #4] 8002518: 6d9a ldr r2, [r3, #88] @ 0x58 800251a: 687b ldr r3, [r7, #4] 800251c: 661a str r2, [r3, #96] @ 0x60 800251e: e00f b.n 8002540 } else { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); 8002520: 687b ldr r3, [r7, #4] 8002522: 681b ldr r3, [r3, #0] 8002524: 4a58 ldr r2, [pc, #352] @ (8002688 ) 8002526: 639a str r2, [r3, #56] @ 0x38 hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; 8002528: 687b ldr r3, [r7, #4] 800252a: 6b9b ldr r3, [r3, #56] @ 0x38 800252c: f043 5280 orr.w r2, r3, #268435456 @ 0x10000000 8002530: 687b ldr r3, [r7, #4] 8002532: 639a str r2, [r3, #56] @ 0x38 hsd->State = HAL_SD_STATE_READY; 8002534: 687b ldr r3, [r7, #4] 8002536: 2201 movs r2, #1 8002538: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_ERROR; 800253c: 2301 movs r3, #1 800253e: e09d b.n 800267c } pCSD->EraseGrSize = (uint8_t)((hsd->CSD[2] & 0x00004000U) >> 14U); 8002540: 687b ldr r3, [r7, #4] 8002542: 6edb ldr r3, [r3, #108] @ 0x6c 8002544: 0b9b lsrs r3, r3, #14 8002546: b2db uxtb r3, r3 8002548: f003 0301 and.w r3, r3, #1 800254c: b2da uxtb r2, r3 800254e: 683b ldr r3, [r7, #0] 8002550: 765a strb r2, [r3, #25] pCSD->EraseGrMul = (uint8_t)((hsd->CSD[2] & 0x00003F80U) >> 7U); 8002552: 687b ldr r3, [r7, #4] 8002554: 6edb ldr r3, [r3, #108] @ 0x6c 8002556: 09db lsrs r3, r3, #7 8002558: b2db uxtb r3, r3 800255a: f003 037f and.w r3, r3, #127 @ 0x7f 800255e: b2da uxtb r2, r3 8002560: 683b ldr r3, [r7, #0] 8002562: 769a strb r2, [r3, #26] pCSD->WrProtectGrSize = (uint8_t)(hsd->CSD[2] & 0x0000007FU); 8002564: 687b ldr r3, [r7, #4] 8002566: 6edb ldr r3, [r3, #108] @ 0x6c 8002568: b2db uxtb r3, r3 800256a: f003 037f and.w r3, r3, #127 @ 0x7f 800256e: b2da uxtb r2, r3 8002570: 683b ldr r3, [r7, #0] 8002572: 76da strb r2, [r3, #27] pCSD->WrProtectGrEnable = (uint8_t)((hsd->CSD[3] & 0x80000000U) >> 31U); 8002574: 687b ldr r3, [r7, #4] 8002576: 6f1b ldr r3, [r3, #112] @ 0x70 8002578: 0fdb lsrs r3, r3, #31 800257a: b2da uxtb r2, r3 800257c: 683b ldr r3, [r7, #0] 800257e: 771a strb r2, [r3, #28] pCSD->ManDeflECC = (uint8_t)((hsd->CSD[3] & 0x60000000U) >> 29U); 8002580: 687b ldr r3, [r7, #4] 8002582: 6f1b ldr r3, [r3, #112] @ 0x70 8002584: 0f5b lsrs r3, r3, #29 8002586: b2db uxtb r3, r3 8002588: f003 0303 and.w r3, r3, #3 800258c: b2da uxtb r2, r3 800258e: 683b ldr r3, [r7, #0] 8002590: 775a strb r2, [r3, #29] pCSD->WrSpeedFact = (uint8_t)((hsd->CSD[3] & 0x1C000000U) >> 26U); 8002592: 687b ldr r3, [r7, #4] 8002594: 6f1b ldr r3, [r3, #112] @ 0x70 8002596: 0e9b lsrs r3, r3, #26 8002598: b2db uxtb r3, r3 800259a: f003 0307 and.w r3, r3, #7 800259e: b2da uxtb r2, r3 80025a0: 683b ldr r3, [r7, #0] 80025a2: 779a strb r2, [r3, #30] pCSD->MaxWrBlockLen= (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U); 80025a4: 687b ldr r3, [r7, #4] 80025a6: 6f1b ldr r3, [r3, #112] @ 0x70 80025a8: 0d9b lsrs r3, r3, #22 80025aa: b2db uxtb r3, r3 80025ac: f003 030f and.w r3, r3, #15 80025b0: b2da uxtb r2, r3 80025b2: 683b ldr r3, [r7, #0] 80025b4: 77da strb r2, [r3, #31] pCSD->WriteBlockPaPartial = (uint8_t)((hsd->CSD[3] & 0x00200000U) >> 21U); 80025b6: 687b ldr r3, [r7, #4] 80025b8: 6f1b ldr r3, [r3, #112] @ 0x70 80025ba: 0d5b lsrs r3, r3, #21 80025bc: b2db uxtb r3, r3 80025be: f003 0301 and.w r3, r3, #1 80025c2: b2da uxtb r2, r3 80025c4: 683b ldr r3, [r7, #0] 80025c6: f883 2020 strb.w r2, [r3, #32] pCSD->Reserved3 = 0; 80025ca: 683b ldr r3, [r7, #0] 80025cc: 2200 movs r2, #0 80025ce: f883 2021 strb.w r2, [r3, #33] @ 0x21 pCSD->ContentProtectAppli = (uint8_t)((hsd->CSD[3] & 0x00010000U) >> 16U); 80025d2: 687b ldr r3, [r7, #4] 80025d4: 6f1b ldr r3, [r3, #112] @ 0x70 80025d6: 0c1b lsrs r3, r3, #16 80025d8: b2db uxtb r3, r3 80025da: f003 0301 and.w r3, r3, #1 80025de: b2da uxtb r2, r3 80025e0: 683b ldr r3, [r7, #0] 80025e2: f883 2022 strb.w r2, [r3, #34] @ 0x22 pCSD->FileFormatGroup = (uint8_t)((hsd->CSD[3] & 0x00008000U) >> 15U); 80025e6: 687b ldr r3, [r7, #4] 80025e8: 6f1b ldr r3, [r3, #112] @ 0x70 80025ea: 0bdb lsrs r3, r3, #15 80025ec: b2db uxtb r3, r3 80025ee: f003 0301 and.w r3, r3, #1 80025f2: b2da uxtb r2, r3 80025f4: 683b ldr r3, [r7, #0] 80025f6: f883 2023 strb.w r2, [r3, #35] @ 0x23 pCSD->CopyFlag = (uint8_t)((hsd->CSD[3] & 0x00004000U) >> 14U); 80025fa: 687b ldr r3, [r7, #4] 80025fc: 6f1b ldr r3, [r3, #112] @ 0x70 80025fe: 0b9b lsrs r3, r3, #14 8002600: b2db uxtb r3, r3 8002602: f003 0301 and.w r3, r3, #1 8002606: b2da uxtb r2, r3 8002608: 683b ldr r3, [r7, #0] 800260a: f883 2024 strb.w r2, [r3, #36] @ 0x24 pCSD->PermWrProtect = (uint8_t)((hsd->CSD[3] & 0x00002000U) >> 13U); 800260e: 687b ldr r3, [r7, #4] 8002610: 6f1b ldr r3, [r3, #112] @ 0x70 8002612: 0b5b lsrs r3, r3, #13 8002614: b2db uxtb r3, r3 8002616: f003 0301 and.w r3, r3, #1 800261a: b2da uxtb r2, r3 800261c: 683b ldr r3, [r7, #0] 800261e: f883 2025 strb.w r2, [r3, #37] @ 0x25 pCSD->TempWrProtect = (uint8_t)((hsd->CSD[3] & 0x00001000U) >> 12U); 8002622: 687b ldr r3, [r7, #4] 8002624: 6f1b ldr r3, [r3, #112] @ 0x70 8002626: 0b1b lsrs r3, r3, #12 8002628: b2db uxtb r3, r3 800262a: f003 0301 and.w r3, r3, #1 800262e: b2da uxtb r2, r3 8002630: 683b ldr r3, [r7, #0] 8002632: f883 2026 strb.w r2, [r3, #38] @ 0x26 pCSD->FileFormat = (uint8_t)((hsd->CSD[3] & 0x00000C00U) >> 10U); 8002636: 687b ldr r3, [r7, #4] 8002638: 6f1b ldr r3, [r3, #112] @ 0x70 800263a: 0a9b lsrs r3, r3, #10 800263c: b2db uxtb r3, r3 800263e: f003 0303 and.w r3, r3, #3 8002642: b2da uxtb r2, r3 8002644: 683b ldr r3, [r7, #0] 8002646: f883 2027 strb.w r2, [r3, #39] @ 0x27 pCSD->ECC= (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U); 800264a: 687b ldr r3, [r7, #4] 800264c: 6f1b ldr r3, [r3, #112] @ 0x70 800264e: 0a1b lsrs r3, r3, #8 8002650: b2db uxtb r3, r3 8002652: f003 0303 and.w r3, r3, #3 8002656: b2da uxtb r2, r3 8002658: 683b ldr r3, [r7, #0] 800265a: f883 2028 strb.w r2, [r3, #40] @ 0x28 pCSD->CSD_CRC = (uint8_t)((hsd->CSD[3] & 0x000000FEU) >> 1U); 800265e: 687b ldr r3, [r7, #4] 8002660: 6f1b ldr r3, [r3, #112] @ 0x70 8002662: 085b lsrs r3, r3, #1 8002664: b2db uxtb r3, r3 8002666: f003 037f and.w r3, r3, #127 @ 0x7f 800266a: b2da uxtb r2, r3 800266c: 683b ldr r3, [r7, #0] 800266e: f883 2029 strb.w r2, [r3, #41] @ 0x29 pCSD->Reserved4 = 1; 8002672: 683b ldr r3, [r7, #0] 8002674: 2201 movs r2, #1 8002676: f883 202a strb.w r2, [r3, #42] @ 0x2a return HAL_OK; 800267a: 2300 movs r3, #0 } 800267c: 4618 mov r0, r3 800267e: 370c adds r7, #12 8002680: 46bd mov sp, r7 8002682: bc80 pop {r7} 8002684: 4770 bx lr 8002686: bf00 nop 8002688: 004005ff .word 0x004005ff 0800268c : * @param pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that * will contain the SD card status information * @retval HAL status */ HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo) { 800268c: b480 push {r7} 800268e: b083 sub sp, #12 8002690: af00 add r7, sp, #0 8002692: 6078 str r0, [r7, #4] 8002694: 6039 str r1, [r7, #0] pCardInfo->CardType = (uint32_t)(hsd->SdCard.CardType); 8002696: 687b ldr r3, [r7, #4] 8002698: 6c5a ldr r2, [r3, #68] @ 0x44 800269a: 683b ldr r3, [r7, #0] 800269c: 601a str r2, [r3, #0] pCardInfo->CardVersion = (uint32_t)(hsd->SdCard.CardVersion); 800269e: 687b ldr r3, [r7, #4] 80026a0: 6c9a ldr r2, [r3, #72] @ 0x48 80026a2: 683b ldr r3, [r7, #0] 80026a4: 605a str r2, [r3, #4] pCardInfo->Class = (uint32_t)(hsd->SdCard.Class); 80026a6: 687b ldr r3, [r7, #4] 80026a8: 6cda ldr r2, [r3, #76] @ 0x4c 80026aa: 683b ldr r3, [r7, #0] 80026ac: 609a str r2, [r3, #8] pCardInfo->RelCardAdd = (uint32_t)(hsd->SdCard.RelCardAdd); 80026ae: 687b ldr r3, [r7, #4] 80026b0: 6d1a ldr r2, [r3, #80] @ 0x50 80026b2: 683b ldr r3, [r7, #0] 80026b4: 60da str r2, [r3, #12] pCardInfo->BlockNbr = (uint32_t)(hsd->SdCard.BlockNbr); 80026b6: 687b ldr r3, [r7, #4] 80026b8: 6d5a ldr r2, [r3, #84] @ 0x54 80026ba: 683b ldr r3, [r7, #0] 80026bc: 611a str r2, [r3, #16] pCardInfo->BlockSize = (uint32_t)(hsd->SdCard.BlockSize); 80026be: 687b ldr r3, [r7, #4] 80026c0: 6d9a ldr r2, [r3, #88] @ 0x58 80026c2: 683b ldr r3, [r7, #0] 80026c4: 615a str r2, [r3, #20] pCardInfo->LogBlockNbr = (uint32_t)(hsd->SdCard.LogBlockNbr); 80026c6: 687b ldr r3, [r7, #4] 80026c8: 6dda ldr r2, [r3, #92] @ 0x5c 80026ca: 683b ldr r3, [r7, #0] 80026cc: 619a str r2, [r3, #24] pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize); 80026ce: 687b ldr r3, [r7, #4] 80026d0: 6e1a ldr r2, [r3, #96] @ 0x60 80026d2: 683b ldr r3, [r7, #0] 80026d4: 61da str r2, [r3, #28] return HAL_OK; 80026d6: 2300 movs r3, #0 } 80026d8: 4618 mov r0, r3 80026da: 370c adds r7, #12 80026dc: 46bd mov sp, r7 80026de: bc80 pop {r7} 80026e0: 4770 bx lr 080026e2 : * @brief Gets the current sd card data state. * @param hsd: pointer to SD handle * @retval Card state */ HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd) { 80026e2: b580 push {r7, lr} 80026e4: b086 sub sp, #24 80026e6: af00 add r7, sp, #0 80026e8: 6078 str r0, [r7, #4] uint32_t cardstate; uint32_t errorstate; uint32_t resp1 = 0; 80026ea: 2300 movs r3, #0 80026ec: 60fb str r3, [r7, #12] errorstate = SD_SendStatus(hsd, &resp1); 80026ee: f107 030c add.w r3, r7, #12 80026f2: 4619 mov r1, r3 80026f4: 6878 ldr r0, [r7, #4] 80026f6: f000 f971 bl 80029dc 80026fa: 6178 str r0, [r7, #20] if(errorstate != HAL_SD_ERROR_NONE) 80026fc: 697b ldr r3, [r7, #20] 80026fe: 2b00 cmp r3, #0 8002700: d005 beq.n 800270e { hsd->ErrorCode |= errorstate; 8002702: 687b ldr r3, [r7, #4] 8002704: 6b9a ldr r2, [r3, #56] @ 0x38 8002706: 697b ldr r3, [r7, #20] 8002708: 431a orrs r2, r3 800270a: 687b ldr r3, [r7, #4] 800270c: 639a str r2, [r3, #56] @ 0x38 } cardstate = ((resp1 >> 9U) & 0x0FU); 800270e: 68fb ldr r3, [r7, #12] 8002710: 0a5b lsrs r3, r3, #9 8002712: f003 030f and.w r3, r3, #15 8002716: 613b str r3, [r7, #16] return (HAL_SD_CardStateTypeDef)cardstate; 8002718: 693b ldr r3, [r7, #16] } 800271a: 4618 mov r0, r3 800271c: 3718 adds r7, #24 800271e: 46bd mov sp, r7 8002720: bd80 pop {r7, pc} 08002722 : * @brief Initializes the sd card. * @param hsd: Pointer to SD handle * @retval SD Card error state */ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) { 8002722: b5b0 push {r4, r5, r7, lr} 8002724: b094 sub sp, #80 @ 0x50 8002726: af04 add r7, sp, #16 8002728: 6078 str r0, [r7, #4] HAL_SD_CardCSDTypeDef CSD; uint32_t errorstate; uint16_t sd_rca = 1U; 800272a: 2301 movs r3, #1 800272c: 81fb strh r3, [r7, #14] /* Check the power State */ if(SDIO_GetPowerState(hsd->Instance) == 0U) 800272e: 687b ldr r3, [r7, #4] 8002730: 681b ldr r3, [r3, #0] 8002732: 4618 mov r0, r3 8002734: f000 feff bl 8003536 8002738: 4603 mov r3, r0 800273a: 2b00 cmp r3, #0 800273c: d102 bne.n 8002744 { /* Power off */ return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; 800273e: f04f 6380 mov.w r3, #67108864 @ 0x4000000 8002742: e0b8 b.n 80028b6 } if(hsd->SdCard.CardType != CARD_SECURED) 8002744: 687b ldr r3, [r7, #4] 8002746: 6c5b ldr r3, [r3, #68] @ 0x44 8002748: 2b03 cmp r3, #3 800274a: d02f beq.n 80027ac { /* Send CMD2 ALL_SEND_CID */ errorstate = SDMMC_CmdSendCID(hsd->Instance); 800274c: 687b ldr r3, [r7, #4] 800274e: 681b ldr r3, [r3, #0] 8002750: 4618 mov r0, r3 8002752: f001 f8e0 bl 8003916 8002756: 63f8 str r0, [r7, #60] @ 0x3c if(errorstate != HAL_SD_ERROR_NONE) 8002758: 6bfb ldr r3, [r7, #60] @ 0x3c 800275a: 2b00 cmp r3, #0 800275c: d001 beq.n 8002762 { return errorstate; 800275e: 6bfb ldr r3, [r7, #60] @ 0x3c 8002760: e0a9 b.n 80028b6 } else { /* Get Card identification number data */ hsd->CID[0U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP1); 8002762: 687b ldr r3, [r7, #4] 8002764: 681b ldr r3, [r3, #0] 8002766: 2100 movs r1, #0 8002768: 4618 mov r0, r3 800276a: f000 ff26 bl 80035ba 800276e: 4602 mov r2, r0 8002770: 687b ldr r3, [r7, #4] 8002772: 675a str r2, [r3, #116] @ 0x74 hsd->CID[1U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP2); 8002774: 687b ldr r3, [r7, #4] 8002776: 681b ldr r3, [r3, #0] 8002778: 2104 movs r1, #4 800277a: 4618 mov r0, r3 800277c: f000 ff1d bl 80035ba 8002780: 4602 mov r2, r0 8002782: 687b ldr r3, [r7, #4] 8002784: 679a str r2, [r3, #120] @ 0x78 hsd->CID[2U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP3); 8002786: 687b ldr r3, [r7, #4] 8002788: 681b ldr r3, [r3, #0] 800278a: 2108 movs r1, #8 800278c: 4618 mov r0, r3 800278e: f000 ff14 bl 80035ba 8002792: 4602 mov r2, r0 8002794: 687b ldr r3, [r7, #4] 8002796: 67da str r2, [r3, #124] @ 0x7c hsd->CID[3U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4); 8002798: 687b ldr r3, [r7, #4] 800279a: 681b ldr r3, [r3, #0] 800279c: 210c movs r1, #12 800279e: 4618 mov r0, r3 80027a0: f000 ff0b bl 80035ba 80027a4: 4602 mov r2, r0 80027a6: 687b ldr r3, [r7, #4] 80027a8: f8c3 2080 str.w r2, [r3, #128] @ 0x80 } } if(hsd->SdCard.CardType != CARD_SECURED) 80027ac: 687b ldr r3, [r7, #4] 80027ae: 6c5b ldr r3, [r3, #68] @ 0x44 80027b0: 2b03 cmp r3, #3 80027b2: d00d beq.n 80027d0 { /* Send CMD3 SET_REL_ADDR with argument 0 */ /* SD Card publishes its RCA. */ errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca); 80027b4: 687b ldr r3, [r7, #4] 80027b6: 681b ldr r3, [r3, #0] 80027b8: f107 020e add.w r2, r7, #14 80027bc: 4611 mov r1, r2 80027be: 4618 mov r0, r3 80027c0: f001 f8e6 bl 8003990 80027c4: 63f8 str r0, [r7, #60] @ 0x3c if(errorstate != HAL_SD_ERROR_NONE) 80027c6: 6bfb ldr r3, [r7, #60] @ 0x3c 80027c8: 2b00 cmp r3, #0 80027ca: d001 beq.n 80027d0 { return errorstate; 80027cc: 6bfb ldr r3, [r7, #60] @ 0x3c 80027ce: e072 b.n 80028b6 } } if(hsd->SdCard.CardType != CARD_SECURED) 80027d0: 687b ldr r3, [r7, #4] 80027d2: 6c5b ldr r3, [r3, #68] @ 0x44 80027d4: 2b03 cmp r3, #3 80027d6: d036 beq.n 8002846 { /* Get the SD card RCA */ hsd->SdCard.RelCardAdd = sd_rca; 80027d8: 89fb ldrh r3, [r7, #14] 80027da: 461a mov r2, r3 80027dc: 687b ldr r3, [r7, #4] 80027de: 651a str r2, [r3, #80] @ 0x50 /* Send CMD9 SEND_CSD with argument as card's RCA */ errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); 80027e0: 687b ldr r3, [r7, #4] 80027e2: 681a ldr r2, [r3, #0] 80027e4: 687b ldr r3, [r7, #4] 80027e6: 6d1b ldr r3, [r3, #80] @ 0x50 80027e8: 041b lsls r3, r3, #16 80027ea: 4619 mov r1, r3 80027ec: 4610 mov r0, r2 80027ee: f001 f8b0 bl 8003952 80027f2: 63f8 str r0, [r7, #60] @ 0x3c if(errorstate != HAL_SD_ERROR_NONE) 80027f4: 6bfb ldr r3, [r7, #60] @ 0x3c 80027f6: 2b00 cmp r3, #0 80027f8: d001 beq.n 80027fe { return errorstate; 80027fa: 6bfb ldr r3, [r7, #60] @ 0x3c 80027fc: e05b b.n 80028b6 } else { /* Get Card Specific Data */ hsd->CSD[0U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP1); 80027fe: 687b ldr r3, [r7, #4] 8002800: 681b ldr r3, [r3, #0] 8002802: 2100 movs r1, #0 8002804: 4618 mov r0, r3 8002806: f000 fed8 bl 80035ba 800280a: 4602 mov r2, r0 800280c: 687b ldr r3, [r7, #4] 800280e: 665a str r2, [r3, #100] @ 0x64 hsd->CSD[1U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP2); 8002810: 687b ldr r3, [r7, #4] 8002812: 681b ldr r3, [r3, #0] 8002814: 2104 movs r1, #4 8002816: 4618 mov r0, r3 8002818: f000 fecf bl 80035ba 800281c: 4602 mov r2, r0 800281e: 687b ldr r3, [r7, #4] 8002820: 669a str r2, [r3, #104] @ 0x68 hsd->CSD[2U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP3); 8002822: 687b ldr r3, [r7, #4] 8002824: 681b ldr r3, [r3, #0] 8002826: 2108 movs r1, #8 8002828: 4618 mov r0, r3 800282a: f000 fec6 bl 80035ba 800282e: 4602 mov r2, r0 8002830: 687b ldr r3, [r7, #4] 8002832: 66da str r2, [r3, #108] @ 0x6c hsd->CSD[3U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4); 8002834: 687b ldr r3, [r7, #4] 8002836: 681b ldr r3, [r3, #0] 8002838: 210c movs r1, #12 800283a: 4618 mov r0, r3 800283c: f000 febd bl 80035ba 8002840: 4602 mov r2, r0 8002842: 687b ldr r3, [r7, #4] 8002844: 671a str r2, [r3, #112] @ 0x70 } } /* Get the Card Class */ hsd->SdCard.Class = (SDIO_GetResponse(hsd->Instance, SDIO_RESP2) >> 20U); 8002846: 687b ldr r3, [r7, #4] 8002848: 681b ldr r3, [r3, #0] 800284a: 2104 movs r1, #4 800284c: 4618 mov r0, r3 800284e: f000 feb4 bl 80035ba 8002852: 4603 mov r3, r0 8002854: 0d1a lsrs r2, r3, #20 8002856: 687b ldr r3, [r7, #4] 8002858: 64da str r2, [r3, #76] @ 0x4c /* Get CSD parameters */ if (HAL_SD_GetCardCSD(hsd, &CSD) != HAL_OK) 800285a: f107 0310 add.w r3, r7, #16 800285e: 4619 mov r1, r3 8002860: 6878 ldr r0, [r7, #4] 8002862: f7ff fd6f bl 8002344 8002866: 4603 mov r3, r0 8002868: 2b00 cmp r3, #0 800286a: d002 beq.n 8002872 { return HAL_SD_ERROR_UNSUPPORTED_FEATURE; 800286c: f04f 5380 mov.w r3, #268435456 @ 0x10000000 8002870: e021 b.n 80028b6 } /* Select the Card */ errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16U)); 8002872: 687b ldr r3, [r7, #4] 8002874: 6819 ldr r1, [r3, #0] 8002876: 687b ldr r3, [r7, #4] 8002878: 6d1b ldr r3, [r3, #80] @ 0x50 800287a: 041b lsls r3, r3, #16 800287c: 2200 movs r2, #0 800287e: 461c mov r4, r3 8002880: 4615 mov r5, r2 8002882: 4622 mov r2, r4 8002884: 462b mov r3, r5 8002886: 4608 mov r0, r1 8002888: f000 ffa0 bl 80037cc 800288c: 63f8 str r0, [r7, #60] @ 0x3c if(errorstate != HAL_SD_ERROR_NONE) 800288e: 6bfb ldr r3, [r7, #60] @ 0x3c 8002890: 2b00 cmp r3, #0 8002892: d001 beq.n 8002898 { return errorstate; 8002894: 6bfb ldr r3, [r7, #60] @ 0x3c 8002896: e00e b.n 80028b6 } /* Configure SDIO peripheral interface */ (void)SDIO_Init(hsd->Instance, hsd->Init); 8002898: 687b ldr r3, [r7, #4] 800289a: 681d ldr r5, [r3, #0] 800289c: 687b ldr r3, [r7, #4] 800289e: 466c mov r4, sp 80028a0: f103 0210 add.w r2, r3, #16 80028a4: ca07 ldmia r2, {r0, r1, r2} 80028a6: e884 0007 stmia.w r4, {r0, r1, r2} 80028aa: 3304 adds r3, #4 80028ac: cb0e ldmia r3, {r1, r2, r3} 80028ae: 4628 mov r0, r5 80028b0: f000 fdee bl 8003490 /* All cards are initialized */ return HAL_SD_ERROR_NONE; 80028b4: 2300 movs r3, #0 } 80028b6: 4618 mov r0, r3 80028b8: 3740 adds r7, #64 @ 0x40 80028ba: 46bd mov sp, r7 80028bc: bdb0 pop {r4, r5, r7, pc} ... 080028c0 : * in the SD handle. * @param hsd: Pointer to SD handle * @retval error state */ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) { 80028c0: b580 push {r7, lr} 80028c2: b086 sub sp, #24 80028c4: af00 add r7, sp, #0 80028c6: 6078 str r0, [r7, #4] __IO uint32_t count = 0U; 80028c8: 2300 movs r3, #0 80028ca: 60bb str r3, [r7, #8] uint32_t response = 0U, validvoltage = 0U; 80028cc: 2300 movs r3, #0 80028ce: 617b str r3, [r7, #20] 80028d0: 2300 movs r3, #0 80028d2: 613b str r3, [r7, #16] uint32_t errorstate; /* CMD0: GO_IDLE_STATE */ errorstate = SDMMC_CmdGoIdleState(hsd->Instance); 80028d4: 687b ldr r3, [r7, #4] 80028d6: 681b ldr r3, [r3, #0] 80028d8: 4618 mov r0, r3 80028da: f000 ff9a bl 8003812 80028de: 60f8 str r0, [r7, #12] if(errorstate != HAL_SD_ERROR_NONE) 80028e0: 68fb ldr r3, [r7, #12] 80028e2: 2b00 cmp r3, #0 80028e4: d001 beq.n 80028ea { return errorstate; 80028e6: 68fb ldr r3, [r7, #12] 80028e8: e072 b.n 80029d0 } /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */ errorstate = SDMMC_CmdOperCond(hsd->Instance); 80028ea: 687b ldr r3, [r7, #4] 80028ec: 681b ldr r3, [r3, #0] 80028ee: 4618 mov r0, r3 80028f0: f000 ffad bl 800384e 80028f4: 60f8 str r0, [r7, #12] if(errorstate != HAL_SD_ERROR_NONE) 80028f6: 68fb ldr r3, [r7, #12] 80028f8: 2b00 cmp r3, #0 80028fa: d00d beq.n 8002918 { hsd->SdCard.CardVersion = CARD_V1_X; 80028fc: 687b ldr r3, [r7, #4] 80028fe: 2200 movs r2, #0 8002900: 649a str r2, [r3, #72] @ 0x48 /* CMD0: GO_IDLE_STATE */ errorstate = SDMMC_CmdGoIdleState(hsd->Instance); 8002902: 687b ldr r3, [r7, #4] 8002904: 681b ldr r3, [r3, #0] 8002906: 4618 mov r0, r3 8002908: f000 ff83 bl 8003812 800290c: 60f8 str r0, [r7, #12] if(errorstate != HAL_SD_ERROR_NONE) 800290e: 68fb ldr r3, [r7, #12] 8002910: 2b00 cmp r3, #0 8002912: d004 beq.n 800291e { return errorstate; 8002914: 68fb ldr r3, [r7, #12] 8002916: e05b b.n 80029d0 } } else { hsd->SdCard.CardVersion = CARD_V2_X; 8002918: 687b ldr r3, [r7, #4] 800291a: 2201 movs r2, #1 800291c: 649a str r2, [r3, #72] @ 0x48 } if( hsd->SdCard.CardVersion == CARD_V2_X) 800291e: 687b ldr r3, [r7, #4] 8002920: 6c9b ldr r3, [r3, #72] @ 0x48 8002922: 2b01 cmp r3, #1 8002924: d137 bne.n 8002996 { /* SEND CMD55 APP_CMD with RCA as 0 */ errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); 8002926: 687b ldr r3, [r7, #4] 8002928: 681b ldr r3, [r3, #0] 800292a: 2100 movs r1, #0 800292c: 4618 mov r0, r3 800292e: f000 ffad bl 800388c 8002932: 60f8 str r0, [r7, #12] if(errorstate != HAL_SD_ERROR_NONE) 8002934: 68fb ldr r3, [r7, #12] 8002936: 2b00 cmp r3, #0 8002938: d02d beq.n 8002996 { return HAL_SD_ERROR_UNSUPPORTED_FEATURE; 800293a: f04f 5380 mov.w r3, #268435456 @ 0x10000000 800293e: e047 b.n 80029d0 /* SD CARD */ /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ while((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U)) { /* SEND CMD55 APP_CMD with RCA as 0 */ errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); 8002940: 687b ldr r3, [r7, #4] 8002942: 681b ldr r3, [r3, #0] 8002944: 2100 movs r1, #0 8002946: 4618 mov r0, r3 8002948: f000 ffa0 bl 800388c 800294c: 60f8 str r0, [r7, #12] if(errorstate != HAL_SD_ERROR_NONE) 800294e: 68fb ldr r3, [r7, #12] 8002950: 2b00 cmp r3, #0 8002952: d001 beq.n 8002958 { return errorstate; 8002954: 68fb ldr r3, [r7, #12] 8002956: e03b b.n 80029d0 } /* Send CMD41 */ errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY | SD_SWITCH_1_8V_CAPACITY); 8002958: 687b ldr r3, [r7, #4] 800295a: 681b ldr r3, [r3, #0] 800295c: 491e ldr r1, [pc, #120] @ (80029d8 ) 800295e: 4618 mov r0, r3 8002960: f000 ffb6 bl 80038d0 8002964: 60f8 str r0, [r7, #12] if(errorstate != HAL_SD_ERROR_NONE) 8002966: 68fb ldr r3, [r7, #12] 8002968: 2b00 cmp r3, #0 800296a: d002 beq.n 8002972 { return HAL_SD_ERROR_UNSUPPORTED_FEATURE; 800296c: f04f 5380 mov.w r3, #268435456 @ 0x10000000 8002970: e02e b.n 80029d0 } /* Get command response */ response = SDIO_GetResponse(hsd->Instance, SDIO_RESP1); 8002972: 687b ldr r3, [r7, #4] 8002974: 681b ldr r3, [r3, #0] 8002976: 2100 movs r1, #0 8002978: 4618 mov r0, r3 800297a: f000 fe1e bl 80035ba 800297e: 6178 str r0, [r7, #20] /* Get operating voltage*/ validvoltage = (((response >> 31U) == 1U) ? 1U : 0U); 8002980: 697b ldr r3, [r7, #20] 8002982: 0fdb lsrs r3, r3, #31 8002984: 2b01 cmp r3, #1 8002986: d101 bne.n 800298c 8002988: 2301 movs r3, #1 800298a: e000 b.n 800298e 800298c: 2300 movs r3, #0 800298e: 613b str r3, [r7, #16] count++; 8002990: 68bb ldr r3, [r7, #8] 8002992: 3301 adds r3, #1 8002994: 60bb str r3, [r7, #8] while((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U)) 8002996: 68bb ldr r3, [r7, #8] 8002998: f64f 72fe movw r2, #65534 @ 0xfffe 800299c: 4293 cmp r3, r2 800299e: d802 bhi.n 80029a6 80029a0: 693b ldr r3, [r7, #16] 80029a2: 2b00 cmp r3, #0 80029a4: d0cc beq.n 8002940 } if(count >= SDMMC_MAX_VOLT_TRIAL) 80029a6: 68bb ldr r3, [r7, #8] 80029a8: f64f 72fe movw r2, #65534 @ 0xfffe 80029ac: 4293 cmp r3, r2 80029ae: d902 bls.n 80029b6 { return HAL_SD_ERROR_INVALID_VOLTRANGE; 80029b0: f04f 7380 mov.w r3, #16777216 @ 0x1000000 80029b4: e00c b.n 80029d0 } if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */ 80029b6: 697b ldr r3, [r7, #20] 80029b8: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000 80029bc: 2b00 cmp r3, #0 80029be: d003 beq.n 80029c8 { hsd->SdCard.CardType = CARD_SDHC_SDXC; 80029c0: 687b ldr r3, [r7, #4] 80029c2: 2201 movs r2, #1 80029c4: 645a str r2, [r3, #68] @ 0x44 80029c6: e002 b.n 80029ce } else { hsd->SdCard.CardType = CARD_SDSC; 80029c8: 687b ldr r3, [r7, #4] 80029ca: 2200 movs r2, #0 80029cc: 645a str r2, [r3, #68] @ 0x44 } return HAL_SD_ERROR_NONE; 80029ce: 2300 movs r3, #0 } 80029d0: 4618 mov r0, r3 80029d2: 3718 adds r7, #24 80029d4: 46bd mov sp, r7 80029d6: bd80 pop {r7, pc} 80029d8: c1100000 .word 0xc1100000 080029dc : * @param pCardStatus: pointer to the buffer that will contain the SD card * status (Card Status register) * @retval error state */ static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus) { 80029dc: b580 push {r7, lr} 80029de: b084 sub sp, #16 80029e0: af00 add r7, sp, #0 80029e2: 6078 str r0, [r7, #4] 80029e4: 6039 str r1, [r7, #0] uint32_t errorstate; if(pCardStatus == NULL) 80029e6: 683b ldr r3, [r7, #0] 80029e8: 2b00 cmp r3, #0 80029ea: d102 bne.n 80029f2 { return HAL_SD_ERROR_PARAM; 80029ec: f04f 6300 mov.w r3, #134217728 @ 0x8000000 80029f0: e018 b.n 8002a24 } /* Send Status command */ errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); 80029f2: 687b ldr r3, [r7, #4] 80029f4: 681a ldr r2, [r3, #0] 80029f6: 687b ldr r3, [r7, #4] 80029f8: 6d1b ldr r3, [r3, #80] @ 0x50 80029fa: 041b lsls r3, r3, #16 80029fc: 4619 mov r1, r3 80029fe: 4610 mov r0, r2 8002a00: f000 ffe7 bl 80039d2 8002a04: 60f8 str r0, [r7, #12] if(errorstate != HAL_SD_ERROR_NONE) 8002a06: 68fb ldr r3, [r7, #12] 8002a08: 2b00 cmp r3, #0 8002a0a: d001 beq.n 8002a10 { return errorstate; 8002a0c: 68fb ldr r3, [r7, #12] 8002a0e: e009 b.n 8002a24 } /* Get SD card status */ *pCardStatus = SDIO_GetResponse(hsd->Instance, SDIO_RESP1); 8002a10: 687b ldr r3, [r7, #4] 8002a12: 681b ldr r3, [r3, #0] 8002a14: 2100 movs r1, #0 8002a16: 4618 mov r0, r3 8002a18: f000 fdcf bl 80035ba 8002a1c: 4602 mov r2, r0 8002a1e: 683b ldr r3, [r7, #0] 8002a20: 601a str r2, [r3, #0] return HAL_SD_ERROR_NONE; 8002a22: 2300 movs r3, #0 } 8002a24: 4618 mov r0, r3 8002a26: 3710 adds r7, #16 8002a28: 46bd mov sp, r7 8002a2a: bd80 pop {r7, pc} 08002a2c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8002a2c: b580 push {r7, lr} 8002a2e: b082 sub sp, #8 8002a30: af00 add r7, sp, #0 8002a32: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8002a34: 687b ldr r3, [r7, #4] 8002a36: 2b00 cmp r3, #0 8002a38: d101 bne.n 8002a3e { return HAL_ERROR; 8002a3a: 2301 movs r3, #1 8002a3c: e042 b.n 8002ac4 assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); #if defined(USART_CR1_OVER8) assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); #endif /* USART_CR1_OVER8 */ if (huart->gState == HAL_UART_STATE_RESET) 8002a3e: 687b ldr r3, [r7, #4] 8002a40: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8002a44: b2db uxtb r3, r3 8002a46: 2b00 cmp r3, #0 8002a48: d106 bne.n 8002a58 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 8002a4a: 687b ldr r3, [r7, #4] 8002a4c: 2200 movs r2, #0 8002a4e: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8002a52: 6878 ldr r0, [r7, #4] 8002a54: f7fd fe2c bl 80006b0 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8002a58: 687b ldr r3, [r7, #4] 8002a5a: 2224 movs r2, #36 @ 0x24 8002a5c: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 8002a60: 687b ldr r3, [r7, #4] 8002a62: 681b ldr r3, [r3, #0] 8002a64: 68da ldr r2, [r3, #12] 8002a66: 687b ldr r3, [r7, #4] 8002a68: 681b ldr r3, [r3, #0] 8002a6a: f422 5200 bic.w r2, r2, #8192 @ 0x2000 8002a6e: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 8002a70: 6878 ldr r0, [r7, #4] 8002a72: f000 fc7f bl 8003374 /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8002a76: 687b ldr r3, [r7, #4] 8002a78: 681b ldr r3, [r3, #0] 8002a7a: 691a ldr r2, [r3, #16] 8002a7c: 687b ldr r3, [r7, #4] 8002a7e: 681b ldr r3, [r3, #0] 8002a80: f422 4290 bic.w r2, r2, #18432 @ 0x4800 8002a84: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8002a86: 687b ldr r3, [r7, #4] 8002a88: 681b ldr r3, [r3, #0] 8002a8a: 695a ldr r2, [r3, #20] 8002a8c: 687b ldr r3, [r7, #4] 8002a8e: 681b ldr r3, [r3, #0] 8002a90: f022 022a bic.w r2, r2, #42 @ 0x2a 8002a94: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 8002a96: 687b ldr r3, [r7, #4] 8002a98: 681b ldr r3, [r3, #0] 8002a9a: 68da ldr r2, [r3, #12] 8002a9c: 687b ldr r3, [r7, #4] 8002a9e: 681b ldr r3, [r3, #0] 8002aa0: f442 5200 orr.w r2, r2, #8192 @ 0x2000 8002aa4: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8002aa6: 687b ldr r3, [r7, #4] 8002aa8: 2200 movs r2, #0 8002aaa: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_READY; 8002aac: 687b ldr r3, [r7, #4] 8002aae: 2220 movs r2, #32 8002ab0: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 8002ab4: 687b ldr r3, [r7, #4] 8002ab6: 2220 movs r2, #32 8002ab8: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->RxEventType = HAL_UART_RXEVENT_TC; 8002abc: 687b ldr r3, [r7, #4] 8002abe: 2200 movs r2, #0 8002ac0: 635a str r2, [r3, #52] @ 0x34 return HAL_OK; 8002ac2: 2300 movs r3, #0 } 8002ac4: 4618 mov r0, r3 8002ac6: 3708 adds r7, #8 8002ac8: 46bd mov sp, r7 8002aca: bd80 pop {r7, pc} 08002acc : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 8002acc: b580 push {r7, lr} 8002ace: b0ba sub sp, #232 @ 0xe8 8002ad0: af00 add r7, sp, #0 8002ad2: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->SR); 8002ad4: 687b ldr r3, [r7, #4] 8002ad6: 681b ldr r3, [r3, #0] 8002ad8: 681b ldr r3, [r3, #0] 8002ada: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 8002ade: 687b ldr r3, [r7, #4] 8002ae0: 681b ldr r3, [r3, #0] 8002ae2: 68db ldr r3, [r3, #12] 8002ae4: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 8002ae8: 687b ldr r3, [r7, #4] 8002aea: 681b ldr r3, [r3, #0] 8002aec: 695b ldr r3, [r3, #20] 8002aee: f8c7 30dc str.w r3, [r7, #220] @ 0xdc uint32_t errorflags = 0x00U; 8002af2: 2300 movs r3, #0 8002af4: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 uint32_t dmarequest = 0x00U; 8002af8: 2300 movs r3, #0 8002afa: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); 8002afe: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8002b02: f003 030f and.w r3, r3, #15 8002b06: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 if (errorflags == RESET) 8002b0a: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8002b0e: 2b00 cmp r3, #0 8002b10: d10f bne.n 8002b32 { /* UART in mode Receiver -------------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8002b12: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8002b16: f003 0320 and.w r3, r3, #32 8002b1a: 2b00 cmp r3, #0 8002b1c: d009 beq.n 8002b32 8002b1e: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8002b22: f003 0320 and.w r3, r3, #32 8002b26: 2b00 cmp r3, #0 8002b28: d003 beq.n 8002b32 { UART_Receive_IT(huart); 8002b2a: 6878 ldr r0, [r7, #4] 8002b2c: f000 fb63 bl 80031f6 return; 8002b30: e25b b.n 8002fea } } /* If some errors occur */ if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) 8002b32: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8002b36: 2b00 cmp r3, #0 8002b38: f000 80de beq.w 8002cf8 8002b3c: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8002b40: f003 0301 and.w r3, r3, #1 8002b44: 2b00 cmp r3, #0 8002b46: d106 bne.n 8002b56 || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) 8002b48: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8002b4c: f403 7390 and.w r3, r3, #288 @ 0x120 8002b50: 2b00 cmp r3, #0 8002b52: f000 80d1 beq.w 8002cf8 { /* UART parity error interrupt occurred ----------------------------------*/ if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) 8002b56: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8002b5a: f003 0301 and.w r3, r3, #1 8002b5e: 2b00 cmp r3, #0 8002b60: d00b beq.n 8002b7a 8002b62: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8002b66: f403 7380 and.w r3, r3, #256 @ 0x100 8002b6a: 2b00 cmp r3, #0 8002b6c: d005 beq.n 8002b7a { huart->ErrorCode |= HAL_UART_ERROR_PE; 8002b6e: 687b ldr r3, [r7, #4] 8002b70: 6c5b ldr r3, [r3, #68] @ 0x44 8002b72: f043 0201 orr.w r2, r3, #1 8002b76: 687b ldr r3, [r7, #4] 8002b78: 645a str r2, [r3, #68] @ 0x44 } /* UART noise error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8002b7a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8002b7e: f003 0304 and.w r3, r3, #4 8002b82: 2b00 cmp r3, #0 8002b84: d00b beq.n 8002b9e 8002b86: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8002b8a: f003 0301 and.w r3, r3, #1 8002b8e: 2b00 cmp r3, #0 8002b90: d005 beq.n 8002b9e { huart->ErrorCode |= HAL_UART_ERROR_NE; 8002b92: 687b ldr r3, [r7, #4] 8002b94: 6c5b ldr r3, [r3, #68] @ 0x44 8002b96: f043 0202 orr.w r2, r3, #2 8002b9a: 687b ldr r3, [r7, #4] 8002b9c: 645a str r2, [r3, #68] @ 0x44 } /* UART frame error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8002b9e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8002ba2: f003 0302 and.w r3, r3, #2 8002ba6: 2b00 cmp r3, #0 8002ba8: d00b beq.n 8002bc2 8002baa: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8002bae: f003 0301 and.w r3, r3, #1 8002bb2: 2b00 cmp r3, #0 8002bb4: d005 beq.n 8002bc2 { huart->ErrorCode |= HAL_UART_ERROR_FE; 8002bb6: 687b ldr r3, [r7, #4] 8002bb8: 6c5b ldr r3, [r3, #68] @ 0x44 8002bba: f043 0204 orr.w r2, r3, #4 8002bbe: 687b ldr r3, [r7, #4] 8002bc0: 645a str r2, [r3, #68] @ 0x44 } /* UART Over-Run interrupt occurred --------------------------------------*/ if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) 8002bc2: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8002bc6: f003 0308 and.w r3, r3, #8 8002bca: 2b00 cmp r3, #0 8002bcc: d011 beq.n 8002bf2 8002bce: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8002bd2: f003 0320 and.w r3, r3, #32 8002bd6: 2b00 cmp r3, #0 8002bd8: d105 bne.n 8002be6 || ((cr3its & USART_CR3_EIE) != RESET))) 8002bda: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8002bde: f003 0301 and.w r3, r3, #1 8002be2: 2b00 cmp r3, #0 8002be4: d005 beq.n 8002bf2 { huart->ErrorCode |= HAL_UART_ERROR_ORE; 8002be6: 687b ldr r3, [r7, #4] 8002be8: 6c5b ldr r3, [r3, #68] @ 0x44 8002bea: f043 0208 orr.w r2, r3, #8 8002bee: 687b ldr r3, [r7, #4] 8002bf0: 645a str r2, [r3, #68] @ 0x44 } /* Call UART Error Call back function if need be --------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8002bf2: 687b ldr r3, [r7, #4] 8002bf4: 6c5b ldr r3, [r3, #68] @ 0x44 8002bf6: 2b00 cmp r3, #0 8002bf8: f000 81f2 beq.w 8002fe0 { /* UART in mode Receiver -----------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8002bfc: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8002c00: f003 0320 and.w r3, r3, #32 8002c04: 2b00 cmp r3, #0 8002c06: d008 beq.n 8002c1a 8002c08: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8002c0c: f003 0320 and.w r3, r3, #32 8002c10: 2b00 cmp r3, #0 8002c12: d002 beq.n 8002c1a { UART_Receive_IT(huart); 8002c14: 6878 ldr r0, [r7, #4] 8002c16: f000 faee bl 80031f6 } /* If Overrun error occurs, or if any error occurs in DMA mode reception, consider error as blocking */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 8002c1a: 687b ldr r3, [r7, #4] 8002c1c: 681b ldr r3, [r3, #0] 8002c1e: 695b ldr r3, [r3, #20] 8002c20: f003 0340 and.w r3, r3, #64 @ 0x40 8002c24: 2b00 cmp r3, #0 8002c26: bf14 ite ne 8002c28: 2301 movne r3, #1 8002c2a: 2300 moveq r3, #0 8002c2c: b2db uxtb r3, r3 8002c2e: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) 8002c32: 687b ldr r3, [r7, #4] 8002c34: 6c5b ldr r3, [r3, #68] @ 0x44 8002c36: f003 0308 and.w r3, r3, #8 8002c3a: 2b00 cmp r3, #0 8002c3c: d103 bne.n 8002c46 8002c3e: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 8002c42: 2b00 cmp r3, #0 8002c44: d04f beq.n 8002ce6 { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 8002c46: 6878 ldr r0, [r7, #4] 8002c48: f000 f9f8 bl 800303c /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8002c4c: 687b ldr r3, [r7, #4] 8002c4e: 681b ldr r3, [r3, #0] 8002c50: 695b ldr r3, [r3, #20] 8002c52: f003 0340 and.w r3, r3, #64 @ 0x40 8002c56: 2b00 cmp r3, #0 8002c58: d041 beq.n 8002cde { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8002c5a: 687b ldr r3, [r7, #4] 8002c5c: 681b ldr r3, [r3, #0] 8002c5e: 3314 adds r3, #20 8002c60: f8c7 309c str.w r3, [r7, #156] @ 0x9c */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8002c64: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8002c68: e853 3f00 ldrex r3, [r3] 8002c6c: f8c7 3098 str.w r3, [r7, #152] @ 0x98 return(result); 8002c70: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8002c74: f023 0340 bic.w r3, r3, #64 @ 0x40 8002c78: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 8002c7c: 687b ldr r3, [r7, #4] 8002c7e: 681b ldr r3, [r3, #0] 8002c80: 3314 adds r3, #20 8002c82: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 8002c86: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 8002c8a: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8002c8e: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 8002c92: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 8002c96: e841 2300 strex r3, r2, [r1] 8002c9a: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return(result); 8002c9e: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8002ca2: 2b00 cmp r3, #0 8002ca4: d1d9 bne.n 8002c5a /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) 8002ca6: 687b ldr r3, [r7, #4] 8002ca8: 6bdb ldr r3, [r3, #60] @ 0x3c 8002caa: 2b00 cmp r3, #0 8002cac: d013 beq.n 8002cd6 { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 8002cae: 687b ldr r3, [r7, #4] 8002cb0: 6bdb ldr r3, [r3, #60] @ 0x3c 8002cb2: 4a7e ldr r2, [pc, #504] @ (8002eac ) 8002cb4: 635a str r2, [r3, #52] @ 0x34 if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 8002cb6: 687b ldr r3, [r7, #4] 8002cb8: 6bdb ldr r3, [r3, #60] @ 0x3c 8002cba: 4618 mov r0, r3 8002cbc: f7fe f830 bl 8000d20 8002cc0: 4603 mov r3, r0 8002cc2: 2b00 cmp r3, #0 8002cc4: d016 beq.n 8002cf4 { /* Call Directly XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 8002cc6: 687b ldr r3, [r7, #4] 8002cc8: 6bdb ldr r3, [r3, #60] @ 0x3c 8002cca: 6b5b ldr r3, [r3, #52] @ 0x34 8002ccc: 687a ldr r2, [r7, #4] 8002cce: 6bd2 ldr r2, [r2, #60] @ 0x3c 8002cd0: 4610 mov r0, r2 8002cd2: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8002cd4: e00e b.n 8002cf4 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8002cd6: 6878 ldr r0, [r7, #4] 8002cd8: f000 f99c bl 8003014 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8002cdc: e00a b.n 8002cf4 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8002cde: 6878 ldr r0, [r7, #4] 8002ce0: f000 f998 bl 8003014 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8002ce4: e006 b.n 8002cf4 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8002ce6: 6878 ldr r0, [r7, #4] 8002ce8: f000 f994 bl 8003014 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8002cec: 687b ldr r3, [r7, #4] 8002cee: 2200 movs r2, #0 8002cf0: 645a str r2, [r3, #68] @ 0x44 } } return; 8002cf2: e175 b.n 8002fe0 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8002cf4: bf00 nop return; 8002cf6: e173 b.n 8002fe0 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8002cf8: 687b ldr r3, [r7, #4] 8002cfa: 6b1b ldr r3, [r3, #48] @ 0x30 8002cfc: 2b01 cmp r3, #1 8002cfe: f040 814f bne.w 8002fa0 && ((isrflags & USART_SR_IDLE) != 0U) 8002d02: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8002d06: f003 0310 and.w r3, r3, #16 8002d0a: 2b00 cmp r3, #0 8002d0c: f000 8148 beq.w 8002fa0 && ((cr1its & USART_SR_IDLE) != 0U)) 8002d10: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8002d14: f003 0310 and.w r3, r3, #16 8002d18: 2b00 cmp r3, #0 8002d1a: f000 8141 beq.w 8002fa0 { __HAL_UART_CLEAR_IDLEFLAG(huart); 8002d1e: 2300 movs r3, #0 8002d20: 60bb str r3, [r7, #8] 8002d22: 687b ldr r3, [r7, #4] 8002d24: 681b ldr r3, [r3, #0] 8002d26: 681b ldr r3, [r3, #0] 8002d28: 60bb str r3, [r7, #8] 8002d2a: 687b ldr r3, [r7, #4] 8002d2c: 681b ldr r3, [r3, #0] 8002d2e: 685b ldr r3, [r3, #4] 8002d30: 60bb str r3, [r7, #8] 8002d32: 68bb ldr r3, [r7, #8] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8002d34: 687b ldr r3, [r7, #4] 8002d36: 681b ldr r3, [r3, #0] 8002d38: 695b ldr r3, [r3, #20] 8002d3a: f003 0340 and.w r3, r3, #64 @ 0x40 8002d3e: 2b00 cmp r3, #0 8002d40: f000 80b6 beq.w 8002eb0 { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 8002d44: 687b ldr r3, [r7, #4] 8002d46: 6bdb ldr r3, [r3, #60] @ 0x3c 8002d48: 681b ldr r3, [r3, #0] 8002d4a: 685b ldr r3, [r3, #4] 8002d4c: f8a7 30be strh.w r3, [r7, #190] @ 0xbe if ((nb_remaining_rx_data > 0U) 8002d50: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe 8002d54: 2b00 cmp r3, #0 8002d56: f000 8145 beq.w 8002fe4 && (nb_remaining_rx_data < huart->RxXferSize)) 8002d5a: 687b ldr r3, [r7, #4] 8002d5c: 8d9b ldrh r3, [r3, #44] @ 0x2c 8002d5e: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8002d62: 429a cmp r2, r3 8002d64: f080 813e bcs.w 8002fe4 { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 8002d68: 687b ldr r3, [r7, #4] 8002d6a: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8002d6e: 85da strh r2, [r3, #46] @ 0x2e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 8002d70: 687b ldr r3, [r7, #4] 8002d72: 6bdb ldr r3, [r3, #60] @ 0x3c 8002d74: 699b ldr r3, [r3, #24] 8002d76: 2b20 cmp r3, #32 8002d78: f000 8088 beq.w 8002e8c { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8002d7c: 687b ldr r3, [r7, #4] 8002d7e: 681b ldr r3, [r3, #0] 8002d80: 330c adds r3, #12 8002d82: f8c7 3088 str.w r3, [r7, #136] @ 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8002d86: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 8002d8a: e853 3f00 ldrex r3, [r3] 8002d8e: f8c7 3084 str.w r3, [r7, #132] @ 0x84 return(result); 8002d92: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8002d96: f423 7380 bic.w r3, r3, #256 @ 0x100 8002d9a: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 8002d9e: 687b ldr r3, [r7, #4] 8002da0: 681b ldr r3, [r3, #0] 8002da2: 330c adds r3, #12 8002da4: f8d7 20b8 ldr.w r2, [r7, #184] @ 0xb8 8002da8: f8c7 2094 str.w r2, [r7, #148] @ 0x94 8002dac: f8c7 3090 str.w r3, [r7, #144] @ 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8002db0: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 8002db4: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 8002db8: e841 2300 strex r3, r2, [r1] 8002dbc: f8c7 308c str.w r3, [r7, #140] @ 0x8c return(result); 8002dc0: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8002dc4: 2b00 cmp r3, #0 8002dc6: d1d9 bne.n 8002d7c ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8002dc8: 687b ldr r3, [r7, #4] 8002dca: 681b ldr r3, [r3, #0] 8002dcc: 3314 adds r3, #20 8002dce: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8002dd0: 6f7b ldr r3, [r7, #116] @ 0x74 8002dd2: e853 3f00 ldrex r3, [r3] 8002dd6: 673b str r3, [r7, #112] @ 0x70 return(result); 8002dd8: 6f3b ldr r3, [r7, #112] @ 0x70 8002dda: f023 0301 bic.w r3, r3, #1 8002dde: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8002de2: 687b ldr r3, [r7, #4] 8002de4: 681b ldr r3, [r3, #0] 8002de6: 3314 adds r3, #20 8002de8: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8002dec: f8c7 2080 str.w r2, [r7, #128] @ 0x80 8002df0: 67fb str r3, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8002df2: 6ff9 ldr r1, [r7, #124] @ 0x7c 8002df4: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 8002df8: e841 2300 strex r3, r2, [r1] 8002dfc: 67bb str r3, [r7, #120] @ 0x78 return(result); 8002dfe: 6fbb ldr r3, [r7, #120] @ 0x78 8002e00: 2b00 cmp r3, #0 8002e02: d1e1 bne.n 8002dc8 /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8002e04: 687b ldr r3, [r7, #4] 8002e06: 681b ldr r3, [r3, #0] 8002e08: 3314 adds r3, #20 8002e0a: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8002e0c: 6e3b ldr r3, [r7, #96] @ 0x60 8002e0e: e853 3f00 ldrex r3, [r3] 8002e12: 65fb str r3, [r7, #92] @ 0x5c return(result); 8002e14: 6dfb ldr r3, [r7, #92] @ 0x5c 8002e16: f023 0340 bic.w r3, r3, #64 @ 0x40 8002e1a: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 8002e1e: 687b ldr r3, [r7, #4] 8002e20: 681b ldr r3, [r3, #0] 8002e22: 3314 adds r3, #20 8002e24: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 8002e28: 66fa str r2, [r7, #108] @ 0x6c 8002e2a: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8002e2c: 6eb9 ldr r1, [r7, #104] @ 0x68 8002e2e: 6efa ldr r2, [r7, #108] @ 0x6c 8002e30: e841 2300 strex r3, r2, [r1] 8002e34: 667b str r3, [r7, #100] @ 0x64 return(result); 8002e36: 6e7b ldr r3, [r7, #100] @ 0x64 8002e38: 2b00 cmp r3, #0 8002e3a: d1e3 bne.n 8002e04 /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8002e3c: 687b ldr r3, [r7, #4] 8002e3e: 2220 movs r2, #32 8002e40: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8002e44: 687b ldr r3, [r7, #4] 8002e46: 2200 movs r2, #0 8002e48: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8002e4a: 687b ldr r3, [r7, #4] 8002e4c: 681b ldr r3, [r3, #0] 8002e4e: 330c adds r3, #12 8002e50: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8002e52: 6cfb ldr r3, [r7, #76] @ 0x4c 8002e54: e853 3f00 ldrex r3, [r3] 8002e58: 64bb str r3, [r7, #72] @ 0x48 return(result); 8002e5a: 6cbb ldr r3, [r7, #72] @ 0x48 8002e5c: f023 0310 bic.w r3, r3, #16 8002e60: f8c7 30ac str.w r3, [r7, #172] @ 0xac 8002e64: 687b ldr r3, [r7, #4] 8002e66: 681b ldr r3, [r3, #0] 8002e68: 330c adds r3, #12 8002e6a: f8d7 20ac ldr.w r2, [r7, #172] @ 0xac 8002e6e: 65ba str r2, [r7, #88] @ 0x58 8002e70: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8002e72: 6d79 ldr r1, [r7, #84] @ 0x54 8002e74: 6dba ldr r2, [r7, #88] @ 0x58 8002e76: e841 2300 strex r3, r2, [r1] 8002e7a: 653b str r3, [r7, #80] @ 0x50 return(result); 8002e7c: 6d3b ldr r3, [r7, #80] @ 0x50 8002e7e: 2b00 cmp r3, #0 8002e80: d1e3 bne.n 8002e4a /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 8002e82: 687b ldr r3, [r7, #4] 8002e84: 6bdb ldr r3, [r3, #60] @ 0x3c 8002e86: 4618 mov r0, r3 8002e88: f7fd ff0f bl 8000caa } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8002e8c: 687b ldr r3, [r7, #4] 8002e8e: 2202 movs r2, #2 8002e90: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 8002e92: 687b ldr r3, [r7, #4] 8002e94: 8d9a ldrh r2, [r3, #44] @ 0x2c 8002e96: 687b ldr r3, [r7, #4] 8002e98: 8ddb ldrh r3, [r3, #46] @ 0x2e 8002e9a: b29b uxth r3, r3 8002e9c: 1ad3 subs r3, r2, r3 8002e9e: b29b uxth r3, r3 8002ea0: 4619 mov r1, r3 8002ea2: 6878 ldr r0, [r7, #4] 8002ea4: f000 f8bf bl 8003026 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; 8002ea8: e09c b.n 8002fe4 8002eaa: bf00 nop 8002eac: 08003101 .word 0x08003101 else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 8002eb0: 687b ldr r3, [r7, #4] 8002eb2: 8d9a ldrh r2, [r3, #44] @ 0x2c 8002eb4: 687b ldr r3, [r7, #4] 8002eb6: 8ddb ldrh r3, [r3, #46] @ 0x2e 8002eb8: b29b uxth r3, r3 8002eba: 1ad3 subs r3, r2, r3 8002ebc: f8a7 30ce strh.w r3, [r7, #206] @ 0xce if ((huart->RxXferCount > 0U) 8002ec0: 687b ldr r3, [r7, #4] 8002ec2: 8ddb ldrh r3, [r3, #46] @ 0x2e 8002ec4: b29b uxth r3, r3 8002ec6: 2b00 cmp r3, #0 8002ec8: f000 808e beq.w 8002fe8 && (nb_rx_data > 0U)) 8002ecc: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8002ed0: 2b00 cmp r3, #0 8002ed2: f000 8089 beq.w 8002fe8 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8002ed6: 687b ldr r3, [r7, #4] 8002ed8: 681b ldr r3, [r3, #0] 8002eda: 330c adds r3, #12 8002edc: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8002ede: 6bbb ldr r3, [r7, #56] @ 0x38 8002ee0: e853 3f00 ldrex r3, [r3] 8002ee4: 637b str r3, [r7, #52] @ 0x34 return(result); 8002ee6: 6b7b ldr r3, [r7, #52] @ 0x34 8002ee8: f423 7390 bic.w r3, r3, #288 @ 0x120 8002eec: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 8002ef0: 687b ldr r3, [r7, #4] 8002ef2: 681b ldr r3, [r3, #0] 8002ef4: 330c adds r3, #12 8002ef6: f8d7 20c8 ldr.w r2, [r7, #200] @ 0xc8 8002efa: 647a str r2, [r7, #68] @ 0x44 8002efc: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8002efe: 6c39 ldr r1, [r7, #64] @ 0x40 8002f00: 6c7a ldr r2, [r7, #68] @ 0x44 8002f02: e841 2300 strex r3, r2, [r1] 8002f06: 63fb str r3, [r7, #60] @ 0x3c return(result); 8002f08: 6bfb ldr r3, [r7, #60] @ 0x3c 8002f0a: 2b00 cmp r3, #0 8002f0c: d1e3 bne.n 8002ed6 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8002f0e: 687b ldr r3, [r7, #4] 8002f10: 681b ldr r3, [r3, #0] 8002f12: 3314 adds r3, #20 8002f14: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8002f16: 6a7b ldr r3, [r7, #36] @ 0x24 8002f18: e853 3f00 ldrex r3, [r3] 8002f1c: 623b str r3, [r7, #32] return(result); 8002f1e: 6a3b ldr r3, [r7, #32] 8002f20: f023 0301 bic.w r3, r3, #1 8002f24: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 8002f28: 687b ldr r3, [r7, #4] 8002f2a: 681b ldr r3, [r3, #0] 8002f2c: 3314 adds r3, #20 8002f2e: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 8002f32: 633a str r2, [r7, #48] @ 0x30 8002f34: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8002f36: 6af9 ldr r1, [r7, #44] @ 0x2c 8002f38: 6b3a ldr r2, [r7, #48] @ 0x30 8002f3a: e841 2300 strex r3, r2, [r1] 8002f3e: 62bb str r3, [r7, #40] @ 0x28 return(result); 8002f40: 6abb ldr r3, [r7, #40] @ 0x28 8002f42: 2b00 cmp r3, #0 8002f44: d1e3 bne.n 8002f0e /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8002f46: 687b ldr r3, [r7, #4] 8002f48: 2220 movs r2, #32 8002f4a: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8002f4e: 687b ldr r3, [r7, #4] 8002f50: 2200 movs r2, #0 8002f52: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8002f54: 687b ldr r3, [r7, #4] 8002f56: 681b ldr r3, [r3, #0] 8002f58: 330c adds r3, #12 8002f5a: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8002f5c: 693b ldr r3, [r7, #16] 8002f5e: e853 3f00 ldrex r3, [r3] 8002f62: 60fb str r3, [r7, #12] return(result); 8002f64: 68fb ldr r3, [r7, #12] 8002f66: f023 0310 bic.w r3, r3, #16 8002f6a: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 8002f6e: 687b ldr r3, [r7, #4] 8002f70: 681b ldr r3, [r3, #0] 8002f72: 330c adds r3, #12 8002f74: f8d7 20c0 ldr.w r2, [r7, #192] @ 0xc0 8002f78: 61fa str r2, [r7, #28] 8002f7a: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8002f7c: 69b9 ldr r1, [r7, #24] 8002f7e: 69fa ldr r2, [r7, #28] 8002f80: e841 2300 strex r3, r2, [r1] 8002f84: 617b str r3, [r7, #20] return(result); 8002f86: 697b ldr r3, [r7, #20] 8002f88: 2b00 cmp r3, #0 8002f8a: d1e3 bne.n 8002f54 /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8002f8c: 687b ldr r3, [r7, #4] 8002f8e: 2202 movs r2, #2 8002f90: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 8002f92: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8002f96: 4619 mov r1, r3 8002f98: 6878 ldr r0, [r7, #4] 8002f9a: f000 f844 bl 8003026 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; 8002f9e: e023 b.n 8002fe8 } } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) 8002fa0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8002fa4: f003 0380 and.w r3, r3, #128 @ 0x80 8002fa8: 2b00 cmp r3, #0 8002faa: d009 beq.n 8002fc0 8002fac: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8002fb0: f003 0380 and.w r3, r3, #128 @ 0x80 8002fb4: 2b00 cmp r3, #0 8002fb6: d003 beq.n 8002fc0 { UART_Transmit_IT(huart); 8002fb8: 6878 ldr r0, [r7, #4] 8002fba: f000 f8b5 bl 8003128 return; 8002fbe: e014 b.n 8002fea } /* UART in mode Transmitter end --------------------------------------------*/ if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) 8002fc0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8002fc4: f003 0340 and.w r3, r3, #64 @ 0x40 8002fc8: 2b00 cmp r3, #0 8002fca: d00e beq.n 8002fea 8002fcc: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8002fd0: f003 0340 and.w r3, r3, #64 @ 0x40 8002fd4: 2b00 cmp r3, #0 8002fd6: d008 beq.n 8002fea { UART_EndTransmit_IT(huart); 8002fd8: 6878 ldr r0, [r7, #4] 8002fda: f000 f8f4 bl 80031c6 return; 8002fde: e004 b.n 8002fea return; 8002fe0: bf00 nop 8002fe2: e002 b.n 8002fea return; 8002fe4: bf00 nop 8002fe6: e000 b.n 8002fea return; 8002fe8: bf00 nop } } 8002fea: 37e8 adds r7, #232 @ 0xe8 8002fec: 46bd mov sp, r7 8002fee: bd80 pop {r7, pc} 08002ff0 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { 8002ff0: b480 push {r7} 8002ff2: b083 sub sp, #12 8002ff4: af00 add r7, sp, #0 8002ff6: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxCpltCallback could be implemented in the user file */ } 8002ff8: bf00 nop 8002ffa: 370c adds r7, #12 8002ffc: 46bd mov sp, r7 8002ffe: bc80 pop {r7} 8003000: 4770 bx lr 08003002 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { 8003002: b480 push {r7} 8003004: b083 sub sp, #12 8003006: af00 add r7, sp, #0 8003008: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxCpltCallback could be implemented in the user file */ } 800300a: bf00 nop 800300c: 370c adds r7, #12 800300e: 46bd mov sp, r7 8003010: bc80 pop {r7} 8003012: 4770 bx lr 08003014 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 8003014: b480 push {r7} 8003016: b083 sub sp, #12 8003018: af00 add r7, sp, #0 800301a: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback could be implemented in the user file */ } 800301c: bf00 nop 800301e: 370c adds r7, #12 8003020: 46bd mov sp, r7 8003022: bc80 pop {r7} 8003024: 4770 bx lr 08003026 : * @param Size Number of data available in application reception buffer (indicates a position in * reception buffer until which, data are available) * @retval None */ __weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { 8003026: b480 push {r7} 8003028: b083 sub sp, #12 800302a: af00 add r7, sp, #0 800302c: 6078 str r0, [r7, #4] 800302e: 460b mov r3, r1 8003030: 807b strh r3, [r7, #2] UNUSED(Size); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_RxEventCallback can be implemented in the user file. */ } 8003032: bf00 nop 8003034: 370c adds r7, #12 8003036: 46bd mov sp, r7 8003038: bc80 pop {r7} 800303a: 4770 bx lr 0800303c : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 800303c: b480 push {r7} 800303e: b095 sub sp, #84 @ 0x54 8003040: af00 add r7, sp, #0 8003042: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8003044: 687b ldr r3, [r7, #4] 8003046: 681b ldr r3, [r3, #0] 8003048: 330c adds r3, #12 800304a: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800304c: 6b7b ldr r3, [r7, #52] @ 0x34 800304e: e853 3f00 ldrex r3, [r3] 8003052: 633b str r3, [r7, #48] @ 0x30 return(result); 8003054: 6b3b ldr r3, [r7, #48] @ 0x30 8003056: f423 7390 bic.w r3, r3, #288 @ 0x120 800305a: 64fb str r3, [r7, #76] @ 0x4c 800305c: 687b ldr r3, [r7, #4] 800305e: 681b ldr r3, [r3, #0] 8003060: 330c adds r3, #12 8003062: 6cfa ldr r2, [r7, #76] @ 0x4c 8003064: 643a str r2, [r7, #64] @ 0x40 8003066: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8003068: 6bf9 ldr r1, [r7, #60] @ 0x3c 800306a: 6c3a ldr r2, [r7, #64] @ 0x40 800306c: e841 2300 strex r3, r2, [r1] 8003070: 63bb str r3, [r7, #56] @ 0x38 return(result); 8003072: 6bbb ldr r3, [r7, #56] @ 0x38 8003074: 2b00 cmp r3, #0 8003076: d1e5 bne.n 8003044 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8003078: 687b ldr r3, [r7, #4] 800307a: 681b ldr r3, [r3, #0] 800307c: 3314 adds r3, #20 800307e: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8003080: 6a3b ldr r3, [r7, #32] 8003082: e853 3f00 ldrex r3, [r3] 8003086: 61fb str r3, [r7, #28] return(result); 8003088: 69fb ldr r3, [r7, #28] 800308a: f023 0301 bic.w r3, r3, #1 800308e: 64bb str r3, [r7, #72] @ 0x48 8003090: 687b ldr r3, [r7, #4] 8003092: 681b ldr r3, [r3, #0] 8003094: 3314 adds r3, #20 8003096: 6cba ldr r2, [r7, #72] @ 0x48 8003098: 62fa str r2, [r7, #44] @ 0x2c 800309a: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800309c: 6ab9 ldr r1, [r7, #40] @ 0x28 800309e: 6afa ldr r2, [r7, #44] @ 0x2c 80030a0: e841 2300 strex r3, r2, [r1] 80030a4: 627b str r3, [r7, #36] @ 0x24 return(result); 80030a6: 6a7b ldr r3, [r7, #36] @ 0x24 80030a8: 2b00 cmp r3, #0 80030aa: d1e5 bne.n 8003078 /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80030ac: 687b ldr r3, [r7, #4] 80030ae: 6b1b ldr r3, [r3, #48] @ 0x30 80030b0: 2b01 cmp r3, #1 80030b2: d119 bne.n 80030e8 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80030b4: 687b ldr r3, [r7, #4] 80030b6: 681b ldr r3, [r3, #0] 80030b8: 330c adds r3, #12 80030ba: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80030bc: 68fb ldr r3, [r7, #12] 80030be: e853 3f00 ldrex r3, [r3] 80030c2: 60bb str r3, [r7, #8] return(result); 80030c4: 68bb ldr r3, [r7, #8] 80030c6: f023 0310 bic.w r3, r3, #16 80030ca: 647b str r3, [r7, #68] @ 0x44 80030cc: 687b ldr r3, [r7, #4] 80030ce: 681b ldr r3, [r3, #0] 80030d0: 330c adds r3, #12 80030d2: 6c7a ldr r2, [r7, #68] @ 0x44 80030d4: 61ba str r2, [r7, #24] 80030d6: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80030d8: 6979 ldr r1, [r7, #20] 80030da: 69ba ldr r2, [r7, #24] 80030dc: e841 2300 strex r3, r2, [r1] 80030e0: 613b str r3, [r7, #16] return(result); 80030e2: 693b ldr r3, [r7, #16] 80030e4: 2b00 cmp r3, #0 80030e6: d1e5 bne.n 80030b4 } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80030e8: 687b ldr r3, [r7, #4] 80030ea: 2220 movs r2, #32 80030ec: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80030f0: 687b ldr r3, [r7, #4] 80030f2: 2200 movs r2, #0 80030f4: 631a str r2, [r3, #48] @ 0x30 } 80030f6: bf00 nop 80030f8: 3754 adds r7, #84 @ 0x54 80030fa: 46bd mov sp, r7 80030fc: bc80 pop {r7} 80030fe: 4770 bx lr 08003100 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 8003100: b580 push {r7, lr} 8003102: b084 sub sp, #16 8003104: af00 add r7, sp, #0 8003106: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8003108: 687b ldr r3, [r7, #4] 800310a: 6a5b ldr r3, [r3, #36] @ 0x24 800310c: 60fb str r3, [r7, #12] huart->RxXferCount = 0x00U; 800310e: 68fb ldr r3, [r7, #12] 8003110: 2200 movs r2, #0 8003112: 85da strh r2, [r3, #46] @ 0x2e huart->TxXferCount = 0x00U; 8003114: 68fb ldr r3, [r7, #12] 8003116: 2200 movs r2, #0 8003118: 84da strh r2, [r3, #38] @ 0x26 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 800311a: 68f8 ldr r0, [r7, #12] 800311c: f7ff ff7a bl 8003014 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8003120: bf00 nop 8003122: 3710 adds r7, #16 8003124: 46bd mov sp, r7 8003126: bd80 pop {r7, pc} 08003128 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { 8003128: b480 push {r7} 800312a: b085 sub sp, #20 800312c: af00 add r7, sp, #0 800312e: 6078 str r0, [r7, #4] const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 8003130: 687b ldr r3, [r7, #4] 8003132: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8003136: b2db uxtb r3, r3 8003138: 2b21 cmp r3, #33 @ 0x21 800313a: d13e bne.n 80031ba { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 800313c: 687b ldr r3, [r7, #4] 800313e: 689b ldr r3, [r3, #8] 8003140: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8003144: d114 bne.n 8003170 8003146: 687b ldr r3, [r7, #4] 8003148: 691b ldr r3, [r3, #16] 800314a: 2b00 cmp r3, #0 800314c: d110 bne.n 8003170 { tmp = (const uint16_t *) huart->pTxBuffPtr; 800314e: 687b ldr r3, [r7, #4] 8003150: 6a1b ldr r3, [r3, #32] 8003152: 60fb str r3, [r7, #12] huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); 8003154: 68fb ldr r3, [r7, #12] 8003156: 881b ldrh r3, [r3, #0] 8003158: 461a mov r2, r3 800315a: 687b ldr r3, [r7, #4] 800315c: 681b ldr r3, [r3, #0] 800315e: f3c2 0208 ubfx r2, r2, #0, #9 8003162: 605a str r2, [r3, #4] huart->pTxBuffPtr += 2U; 8003164: 687b ldr r3, [r7, #4] 8003166: 6a1b ldr r3, [r3, #32] 8003168: 1c9a adds r2, r3, #2 800316a: 687b ldr r3, [r7, #4] 800316c: 621a str r2, [r3, #32] 800316e: e008 b.n 8003182 } else { huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); 8003170: 687b ldr r3, [r7, #4] 8003172: 6a1b ldr r3, [r3, #32] 8003174: 1c59 adds r1, r3, #1 8003176: 687a ldr r2, [r7, #4] 8003178: 6211 str r1, [r2, #32] 800317a: 781a ldrb r2, [r3, #0] 800317c: 687b ldr r3, [r7, #4] 800317e: 681b ldr r3, [r3, #0] 8003180: 605a str r2, [r3, #4] } if (--huart->TxXferCount == 0U) 8003182: 687b ldr r3, [r7, #4] 8003184: 8cdb ldrh r3, [r3, #38] @ 0x26 8003186: b29b uxth r3, r3 8003188: 3b01 subs r3, #1 800318a: b29b uxth r3, r3 800318c: 687a ldr r2, [r7, #4] 800318e: 4619 mov r1, r3 8003190: 84d1 strh r1, [r2, #38] @ 0x26 8003192: 2b00 cmp r3, #0 8003194: d10f bne.n 80031b6 { /* Disable the UART Transmit Data Register Empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); 8003196: 687b ldr r3, [r7, #4] 8003198: 681b ldr r3, [r3, #0] 800319a: 68da ldr r2, [r3, #12] 800319c: 687b ldr r3, [r7, #4] 800319e: 681b ldr r3, [r3, #0] 80031a0: f022 0280 bic.w r2, r2, #128 @ 0x80 80031a4: 60da str r2, [r3, #12] /* Enable the UART Transmit Complete Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TC); 80031a6: 687b ldr r3, [r7, #4] 80031a8: 681b ldr r3, [r3, #0] 80031aa: 68da ldr r2, [r3, #12] 80031ac: 687b ldr r3, [r7, #4] 80031ae: 681b ldr r3, [r3, #0] 80031b0: f042 0240 orr.w r2, r2, #64 @ 0x40 80031b4: 60da str r2, [r3, #12] } return HAL_OK; 80031b6: 2300 movs r3, #0 80031b8: e000 b.n 80031bc } else { return HAL_BUSY; 80031ba: 2302 movs r3, #2 } } 80031bc: 4618 mov r0, r3 80031be: 3714 adds r7, #20 80031c0: 46bd mov sp, r7 80031c2: bc80 pop {r7} 80031c4: 4770 bx lr 080031c6 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 80031c6: b580 push {r7, lr} 80031c8: b082 sub sp, #8 80031ca: af00 add r7, sp, #0 80031cc: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TC); 80031ce: 687b ldr r3, [r7, #4] 80031d0: 681b ldr r3, [r3, #0] 80031d2: 68da ldr r2, [r3, #12] 80031d4: 687b ldr r3, [r7, #4] 80031d6: 681b ldr r3, [r3, #0] 80031d8: f022 0240 bic.w r2, r2, #64 @ 0x40 80031dc: 60da str r2, [r3, #12] /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 80031de: 687b ldr r3, [r7, #4] 80031e0: 2220 movs r2, #32 80031e2: f883 2041 strb.w r2, [r3, #65] @ 0x41 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 80031e6: 6878 ldr r0, [r7, #4] 80031e8: f7ff ff02 bl 8002ff0 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return HAL_OK; 80031ec: 2300 movs r3, #0 } 80031ee: 4618 mov r0, r3 80031f0: 3708 adds r7, #8 80031f2: 46bd mov sp, r7 80031f4: bd80 pop {r7, pc} 080031f6 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) { 80031f6: b580 push {r7, lr} 80031f8: b08c sub sp, #48 @ 0x30 80031fa: af00 add r7, sp, #0 80031fc: 6078 str r0, [r7, #4] uint8_t *pdata8bits; uint16_t *pdata16bits; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 80031fe: 687b ldr r3, [r7, #4] 8003200: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8003204: b2db uxtb r3, r3 8003206: 2b22 cmp r3, #34 @ 0x22 8003208: f040 80ae bne.w 8003368 { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 800320c: 687b ldr r3, [r7, #4] 800320e: 689b ldr r3, [r3, #8] 8003210: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8003214: d117 bne.n 8003246 8003216: 687b ldr r3, [r7, #4] 8003218: 691b ldr r3, [r3, #16] 800321a: 2b00 cmp r3, #0 800321c: d113 bne.n 8003246 { pdata8bits = NULL; 800321e: 2300 movs r3, #0 8003220: 62fb str r3, [r7, #44] @ 0x2c pdata16bits = (uint16_t *) huart->pRxBuffPtr; 8003222: 687b ldr r3, [r7, #4] 8003224: 6a9b ldr r3, [r3, #40] @ 0x28 8003226: 62bb str r3, [r7, #40] @ 0x28 *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); 8003228: 687b ldr r3, [r7, #4] 800322a: 681b ldr r3, [r3, #0] 800322c: 685b ldr r3, [r3, #4] 800322e: b29b uxth r3, r3 8003230: f3c3 0308 ubfx r3, r3, #0, #9 8003234: b29a uxth r2, r3 8003236: 6abb ldr r3, [r7, #40] @ 0x28 8003238: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 800323a: 687b ldr r3, [r7, #4] 800323c: 6a9b ldr r3, [r3, #40] @ 0x28 800323e: 1c9a adds r2, r3, #2 8003240: 687b ldr r3, [r7, #4] 8003242: 629a str r2, [r3, #40] @ 0x28 8003244: e026 b.n 8003294 } else { pdata8bits = (uint8_t *) huart->pRxBuffPtr; 8003246: 687b ldr r3, [r7, #4] 8003248: 6a9b ldr r3, [r3, #40] @ 0x28 800324a: 62fb str r3, [r7, #44] @ 0x2c pdata16bits = NULL; 800324c: 2300 movs r3, #0 800324e: 62bb str r3, [r7, #40] @ 0x28 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) 8003250: 687b ldr r3, [r7, #4] 8003252: 689b ldr r3, [r3, #8] 8003254: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8003258: d007 beq.n 800326a 800325a: 687b ldr r3, [r7, #4] 800325c: 689b ldr r3, [r3, #8] 800325e: 2b00 cmp r3, #0 8003260: d10a bne.n 8003278 8003262: 687b ldr r3, [r7, #4] 8003264: 691b ldr r3, [r3, #16] 8003266: 2b00 cmp r3, #0 8003268: d106 bne.n 8003278 { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); 800326a: 687b ldr r3, [r7, #4] 800326c: 681b ldr r3, [r3, #0] 800326e: 685b ldr r3, [r3, #4] 8003270: b2da uxtb r2, r3 8003272: 6afb ldr r3, [r7, #44] @ 0x2c 8003274: 701a strb r2, [r3, #0] 8003276: e008 b.n 800328a } else { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); 8003278: 687b ldr r3, [r7, #4] 800327a: 681b ldr r3, [r3, #0] 800327c: 685b ldr r3, [r3, #4] 800327e: b2db uxtb r3, r3 8003280: f003 037f and.w r3, r3, #127 @ 0x7f 8003284: b2da uxtb r2, r3 8003286: 6afb ldr r3, [r7, #44] @ 0x2c 8003288: 701a strb r2, [r3, #0] } huart->pRxBuffPtr += 1U; 800328a: 687b ldr r3, [r7, #4] 800328c: 6a9b ldr r3, [r3, #40] @ 0x28 800328e: 1c5a adds r2, r3, #1 8003290: 687b ldr r3, [r7, #4] 8003292: 629a str r2, [r3, #40] @ 0x28 } if (--huart->RxXferCount == 0U) 8003294: 687b ldr r3, [r7, #4] 8003296: 8ddb ldrh r3, [r3, #46] @ 0x2e 8003298: b29b uxth r3, r3 800329a: 3b01 subs r3, #1 800329c: b29b uxth r3, r3 800329e: 687a ldr r2, [r7, #4] 80032a0: 4619 mov r1, r3 80032a2: 85d1 strh r1, [r2, #46] @ 0x2e 80032a4: 2b00 cmp r3, #0 80032a6: d15d bne.n 8003364 { /* Disable the UART Data Register not empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); 80032a8: 687b ldr r3, [r7, #4] 80032aa: 681b ldr r3, [r3, #0] 80032ac: 68da ldr r2, [r3, #12] 80032ae: 687b ldr r3, [r7, #4] 80032b0: 681b ldr r3, [r3, #0] 80032b2: f022 0220 bic.w r2, r2, #32 80032b6: 60da str r2, [r3, #12] /* Disable the UART Parity Error Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); 80032b8: 687b ldr r3, [r7, #4] 80032ba: 681b ldr r3, [r3, #0] 80032bc: 68da ldr r2, [r3, #12] 80032be: 687b ldr r3, [r7, #4] 80032c0: 681b ldr r3, [r3, #0] 80032c2: f422 7280 bic.w r2, r2, #256 @ 0x100 80032c6: 60da str r2, [r3, #12] /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); 80032c8: 687b ldr r3, [r7, #4] 80032ca: 681b ldr r3, [r3, #0] 80032cc: 695a ldr r2, [r3, #20] 80032ce: 687b ldr r3, [r7, #4] 80032d0: 681b ldr r3, [r3, #0] 80032d2: f022 0201 bic.w r2, r2, #1 80032d6: 615a str r2, [r3, #20] /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80032d8: 687b ldr r3, [r7, #4] 80032da: 2220 movs r2, #32 80032dc: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 80032e0: 687b ldr r3, [r7, #4] 80032e2: 2200 movs r2, #0 80032e4: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80032e6: 687b ldr r3, [r7, #4] 80032e8: 6b1b ldr r3, [r3, #48] @ 0x30 80032ea: 2b01 cmp r3, #1 80032ec: d135 bne.n 800335a { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80032ee: 687b ldr r3, [r7, #4] 80032f0: 2200 movs r2, #0 80032f2: 631a str r2, [r3, #48] @ 0x30 /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80032f4: 687b ldr r3, [r7, #4] 80032f6: 681b ldr r3, [r3, #0] 80032f8: 330c adds r3, #12 80032fa: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80032fc: 697b ldr r3, [r7, #20] 80032fe: e853 3f00 ldrex r3, [r3] 8003302: 613b str r3, [r7, #16] return(result); 8003304: 693b ldr r3, [r7, #16] 8003306: f023 0310 bic.w r3, r3, #16 800330a: 627b str r3, [r7, #36] @ 0x24 800330c: 687b ldr r3, [r7, #4] 800330e: 681b ldr r3, [r3, #0] 8003310: 330c adds r3, #12 8003312: 6a7a ldr r2, [r7, #36] @ 0x24 8003314: 623a str r2, [r7, #32] 8003316: 61fb str r3, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8003318: 69f9 ldr r1, [r7, #28] 800331a: 6a3a ldr r2, [r7, #32] 800331c: e841 2300 strex r3, r2, [r1] 8003320: 61bb str r3, [r7, #24] return(result); 8003322: 69bb ldr r3, [r7, #24] 8003324: 2b00 cmp r3, #0 8003326: d1e5 bne.n 80032f4 /* Check if IDLE flag is set */ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) 8003328: 687b ldr r3, [r7, #4] 800332a: 681b ldr r3, [r3, #0] 800332c: 681b ldr r3, [r3, #0] 800332e: f003 0310 and.w r3, r3, #16 8003332: 2b10 cmp r3, #16 8003334: d10a bne.n 800334c { /* Clear IDLE flag in ISR */ __HAL_UART_CLEAR_IDLEFLAG(huart); 8003336: 2300 movs r3, #0 8003338: 60fb str r3, [r7, #12] 800333a: 687b ldr r3, [r7, #4] 800333c: 681b ldr r3, [r3, #0] 800333e: 681b ldr r3, [r3, #0] 8003340: 60fb str r3, [r7, #12] 8003342: 687b ldr r3, [r7, #4] 8003344: 681b ldr r3, [r3, #0] 8003346: 685b ldr r3, [r3, #4] 8003348: 60fb str r3, [r7, #12] 800334a: 68fb ldr r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 800334c: 687b ldr r3, [r7, #4] 800334e: 8d9b ldrh r3, [r3, #44] @ 0x2c 8003350: 4619 mov r1, r3 8003352: 6878 ldr r0, [r7, #4] 8003354: f7ff fe67 bl 8003026 8003358: e002 b.n 8003360 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 800335a: 6878 ldr r0, [r7, #4] 800335c: f7ff fe51 bl 8003002 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return HAL_OK; 8003360: 2300 movs r3, #0 8003362: e002 b.n 800336a } return HAL_OK; 8003364: 2300 movs r3, #0 8003366: e000 b.n 800336a } else { return HAL_BUSY; 8003368: 2302 movs r3, #2 } } 800336a: 4618 mov r0, r3 800336c: 3730 adds r7, #48 @ 0x30 800336e: 46bd mov sp, r7 8003370: bd80 pop {r7, pc} ... 08003374 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 8003374: b580 push {r7, lr} 8003376: b084 sub sp, #16 8003378: af00 add r7, sp, #0 800337a: 6078 str r0, [r7, #4] assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 800337c: 687b ldr r3, [r7, #4] 800337e: 681b ldr r3, [r3, #0] 8003380: 691b ldr r3, [r3, #16] 8003382: f423 5140 bic.w r1, r3, #12288 @ 0x3000 8003386: 687b ldr r3, [r7, #4] 8003388: 68da ldr r2, [r3, #12] 800338a: 687b ldr r3, [r7, #4] 800338c: 681b ldr r3, [r3, #0] 800338e: 430a orrs r2, r1 8003390: 611a str r2, [r3, #16] tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; MODIFY_REG(huart->Instance->CR1, (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); #else tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; 8003392: 687b ldr r3, [r7, #4] 8003394: 689a ldr r2, [r3, #8] 8003396: 687b ldr r3, [r7, #4] 8003398: 691b ldr r3, [r3, #16] 800339a: 431a orrs r2, r3 800339c: 687b ldr r3, [r7, #4] 800339e: 695b ldr r3, [r3, #20] 80033a0: 4313 orrs r3, r2 80033a2: 60bb str r3, [r7, #8] MODIFY_REG(huart->Instance->CR1, 80033a4: 687b ldr r3, [r7, #4] 80033a6: 681b ldr r3, [r3, #0] 80033a8: 68db ldr r3, [r3, #12] 80033aa: f423 53b0 bic.w r3, r3, #5632 @ 0x1600 80033ae: f023 030c bic.w r3, r3, #12 80033b2: 687a ldr r2, [r7, #4] 80033b4: 6812 ldr r2, [r2, #0] 80033b6: 68b9 ldr r1, [r7, #8] 80033b8: 430b orrs r3, r1 80033ba: 60d3 str r3, [r2, #12] tmpreg); #endif /* USART_CR1_OVER8 */ /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 80033bc: 687b ldr r3, [r7, #4] 80033be: 681b ldr r3, [r3, #0] 80033c0: 695b ldr r3, [r3, #20] 80033c2: f423 7140 bic.w r1, r3, #768 @ 0x300 80033c6: 687b ldr r3, [r7, #4] 80033c8: 699a ldr r2, [r3, #24] 80033ca: 687b ldr r3, [r7, #4] 80033cc: 681b ldr r3, [r3, #0] 80033ce: 430a orrs r2, r1 80033d0: 615a str r2, [r3, #20] if(huart->Instance == USART1) 80033d2: 687b ldr r3, [r7, #4] 80033d4: 681b ldr r3, [r3, #0] 80033d6: 4a2c ldr r2, [pc, #176] @ (8003488 ) 80033d8: 4293 cmp r3, r2 80033da: d103 bne.n 80033e4 { pclk = HAL_RCC_GetPCLK2Freq(); 80033dc: f7fe fb64 bl 8001aa8 80033e0: 60f8 str r0, [r7, #12] 80033e2: e002 b.n 80033ea } else { pclk = HAL_RCC_GetPCLK1Freq(); 80033e4: f7fe fb4c bl 8001a80 80033e8: 60f8 str r0, [r7, #12] else { huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } #else huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 80033ea: 68fa ldr r2, [r7, #12] 80033ec: 4613 mov r3, r2 80033ee: 009b lsls r3, r3, #2 80033f0: 4413 add r3, r2 80033f2: 009a lsls r2, r3, #2 80033f4: 441a add r2, r3 80033f6: 687b ldr r3, [r7, #4] 80033f8: 685b ldr r3, [r3, #4] 80033fa: 009b lsls r3, r3, #2 80033fc: fbb2 f3f3 udiv r3, r2, r3 8003400: 4a22 ldr r2, [pc, #136] @ (800348c ) 8003402: fba2 2303 umull r2, r3, r2, r3 8003406: 095b lsrs r3, r3, #5 8003408: 0119 lsls r1, r3, #4 800340a: 68fa ldr r2, [r7, #12] 800340c: 4613 mov r3, r2 800340e: 009b lsls r3, r3, #2 8003410: 4413 add r3, r2 8003412: 009a lsls r2, r3, #2 8003414: 441a add r2, r3 8003416: 687b ldr r3, [r7, #4] 8003418: 685b ldr r3, [r3, #4] 800341a: 009b lsls r3, r3, #2 800341c: fbb2 f2f3 udiv r2, r2, r3 8003420: 4b1a ldr r3, [pc, #104] @ (800348c ) 8003422: fba3 0302 umull r0, r3, r3, r2 8003426: 095b lsrs r3, r3, #5 8003428: 2064 movs r0, #100 @ 0x64 800342a: fb00 f303 mul.w r3, r0, r3 800342e: 1ad3 subs r3, r2, r3 8003430: 011b lsls r3, r3, #4 8003432: 3332 adds r3, #50 @ 0x32 8003434: 4a15 ldr r2, [pc, #84] @ (800348c ) 8003436: fba2 2303 umull r2, r3, r2, r3 800343a: 095b lsrs r3, r3, #5 800343c: f003 03f0 and.w r3, r3, #240 @ 0xf0 8003440: 4419 add r1, r3 8003442: 68fa ldr r2, [r7, #12] 8003444: 4613 mov r3, r2 8003446: 009b lsls r3, r3, #2 8003448: 4413 add r3, r2 800344a: 009a lsls r2, r3, #2 800344c: 441a add r2, r3 800344e: 687b ldr r3, [r7, #4] 8003450: 685b ldr r3, [r3, #4] 8003452: 009b lsls r3, r3, #2 8003454: fbb2 f2f3 udiv r2, r2, r3 8003458: 4b0c ldr r3, [pc, #48] @ (800348c ) 800345a: fba3 0302 umull r0, r3, r3, r2 800345e: 095b lsrs r3, r3, #5 8003460: 2064 movs r0, #100 @ 0x64 8003462: fb00 f303 mul.w r3, r0, r3 8003466: 1ad3 subs r3, r2, r3 8003468: 011b lsls r3, r3, #4 800346a: 3332 adds r3, #50 @ 0x32 800346c: 4a07 ldr r2, [pc, #28] @ (800348c ) 800346e: fba2 2303 umull r2, r3, r2, r3 8003472: 095b lsrs r3, r3, #5 8003474: f003 020f and.w r2, r3, #15 8003478: 687b ldr r3, [r7, #4] 800347a: 681b ldr r3, [r3, #0] 800347c: 440a add r2, r1 800347e: 609a str r2, [r3, #8] #endif /* USART_CR1_OVER8 */ } 8003480: bf00 nop 8003482: 3710 adds r7, #16 8003484: 46bd mov sp, r7 8003486: bd80 pop {r7, pc} 8003488: 40013800 .word 0x40013800 800348c: 51eb851f .word 0x51eb851f 08003490 : * @param SDIOx: Pointer to SDMMC register base * @param Init: SDMMC initialization structure * @retval HAL status */ HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init) { 8003490: b084 sub sp, #16 8003492: b480 push {r7} 8003494: b085 sub sp, #20 8003496: af00 add r7, sp, #0 8003498: 6078 str r0, [r7, #4] 800349a: f107 001c add.w r0, r7, #28 800349e: e880 000e stmia.w r0, {r1, r2, r3} uint32_t tmpreg = 0; 80034a2: 2300 movs r3, #0 80034a4: 60fb str r3, [r7, #12] assert_param(IS_SDIO_BUS_WIDE(Init.BusWide)); assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl)); assert_param(IS_SDIO_CLKDIV(Init.ClockDiv)); /* Set SDMMC configuration parameters */ tmpreg |= (Init.ClockEdge |\ 80034a6: 69fa ldr r2, [r7, #28] Init.ClockBypass |\ 80034a8: 6a3b ldr r3, [r7, #32] tmpreg |= (Init.ClockEdge |\ 80034aa: 431a orrs r2, r3 Init.ClockPowerSave |\ 80034ac: 6a7b ldr r3, [r7, #36] @ 0x24 Init.ClockBypass |\ 80034ae: 431a orrs r2, r3 Init.BusWide |\ 80034b0: 6abb ldr r3, [r7, #40] @ 0x28 Init.ClockPowerSave |\ 80034b2: 431a orrs r2, r3 Init.HardwareFlowControl |\ 80034b4: 6afb ldr r3, [r7, #44] @ 0x2c Init.BusWide |\ 80034b6: 431a orrs r2, r3 Init.ClockDiv 80034b8: 6b3b ldr r3, [r7, #48] @ 0x30 Init.HardwareFlowControl |\ 80034ba: 4313 orrs r3, r2 tmpreg |= (Init.ClockEdge |\ 80034bc: 68fa ldr r2, [r7, #12] 80034be: 4313 orrs r3, r2 80034c0: 60fb str r3, [r7, #12] ); /* Write to SDMMC CLKCR */ MODIFY_REG(SDIOx->CLKCR, CLKCR_CLEAR_MASK, tmpreg); 80034c2: 687b ldr r3, [r7, #4] 80034c4: 685b ldr r3, [r3, #4] 80034c6: f423 43fd bic.w r3, r3, #32384 @ 0x7e80 80034ca: f023 037f bic.w r3, r3, #127 @ 0x7f 80034ce: 68fa ldr r2, [r7, #12] 80034d0: 431a orrs r2, r3 80034d2: 687b ldr r3, [r7, #4] 80034d4: 605a str r2, [r3, #4] return HAL_OK; 80034d6: 2300 movs r3, #0 } 80034d8: 4618 mov r0, r3 80034da: 3714 adds r7, #20 80034dc: 46bd mov sp, r7 80034de: bc80 pop {r7} 80034e0: b004 add sp, #16 80034e2: 4770 bx lr 080034e4 : * @brief Read data (word) from Rx FIFO in blocking mode (polling) * @param SDIOx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx) { 80034e4: b480 push {r7} 80034e6: b083 sub sp, #12 80034e8: af00 add r7, sp, #0 80034ea: 6078 str r0, [r7, #4] /* Read data from Rx FIFO */ return (SDIOx->FIFO); 80034ec: 687b ldr r3, [r7, #4] 80034ee: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 } 80034f2: 4618 mov r0, r3 80034f4: 370c adds r7, #12 80034f6: 46bd mov sp, r7 80034f8: bc80 pop {r7} 80034fa: 4770 bx lr 080034fc : * @param SDIOx: Pointer to SDMMC register base * @param pWriteData: pointer to data to write * @retval HAL status */ HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData) { 80034fc: b480 push {r7} 80034fe: b083 sub sp, #12 8003500: af00 add r7, sp, #0 8003502: 6078 str r0, [r7, #4] 8003504: 6039 str r1, [r7, #0] /* Write data to FIFO */ SDIOx->FIFO = *pWriteData; 8003506: 683b ldr r3, [r7, #0] 8003508: 681a ldr r2, [r3, #0] 800350a: 687b ldr r3, [r7, #4] 800350c: f8c3 2080 str.w r2, [r3, #128] @ 0x80 return HAL_OK; 8003510: 2300 movs r3, #0 } 8003512: 4618 mov r0, r3 8003514: 370c adds r7, #12 8003516: 46bd mov sp, r7 8003518: bc80 pop {r7} 800351a: 4770 bx lr 0800351c : * @brief Set SDMMC Power state to ON. * @param SDIOx: Pointer to SDMMC register base * @retval HAL status */ HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx) { 800351c: b480 push {r7} 800351e: b083 sub sp, #12 8003520: af00 add r7, sp, #0 8003522: 6078 str r0, [r7, #4] /* Set power state to ON */ SDIOx->POWER = SDIO_POWER_PWRCTRL; 8003524: 687b ldr r3, [r7, #4] 8003526: 2203 movs r2, #3 8003528: 601a str r2, [r3, #0] return HAL_OK; 800352a: 2300 movs r3, #0 } 800352c: 4618 mov r0, r3 800352e: 370c adds r7, #12 8003530: 46bd mov sp, r7 8003532: bc80 pop {r7} 8003534: 4770 bx lr 08003536 : * - 0x00: Power OFF * - 0x02: Power UP * - 0x03: Power ON */ uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx) { 8003536: b480 push {r7} 8003538: b083 sub sp, #12 800353a: af00 add r7, sp, #0 800353c: 6078 str r0, [r7, #4] return (SDIOx->POWER & SDIO_POWER_PWRCTRL); 800353e: 687b ldr r3, [r7, #4] 8003540: 681b ldr r3, [r3, #0] 8003542: f003 0303 and.w r3, r3, #3 } 8003546: 4618 mov r0, r3 8003548: 370c adds r7, #12 800354a: 46bd mov sp, r7 800354c: bc80 pop {r7} 800354e: 4770 bx lr 08003550 : * @param Command: pointer to a SDIO_CmdInitTypeDef structure that contains * the configuration information for the SDMMC command * @retval HAL status */ HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command) { 8003550: b480 push {r7} 8003552: b085 sub sp, #20 8003554: af00 add r7, sp, #0 8003556: 6078 str r0, [r7, #4] 8003558: 6039 str r1, [r7, #0] uint32_t tmpreg = 0; 800355a: 2300 movs r3, #0 800355c: 60fb str r3, [r7, #12] assert_param(IS_SDIO_RESPONSE(Command->Response)); assert_param(IS_SDIO_WAIT(Command->WaitForInterrupt)); assert_param(IS_SDIO_CPSM(Command->CPSM)); /* Set the SDMMC Argument value */ SDIOx->ARG = Command->Argument; 800355e: 683b ldr r3, [r7, #0] 8003560: 681a ldr r2, [r3, #0] 8003562: 687b ldr r3, [r7, #4] 8003564: 609a str r2, [r3, #8] /* Set SDMMC command parameters */ tmpreg |= (uint32_t)(Command->CmdIndex |\ 8003566: 683b ldr r3, [r7, #0] 8003568: 685a ldr r2, [r3, #4] Command->Response |\ 800356a: 683b ldr r3, [r7, #0] 800356c: 689b ldr r3, [r3, #8] tmpreg |= (uint32_t)(Command->CmdIndex |\ 800356e: 431a orrs r2, r3 Command->WaitForInterrupt |\ 8003570: 683b ldr r3, [r7, #0] 8003572: 68db ldr r3, [r3, #12] Command->Response |\ 8003574: 431a orrs r2, r3 Command->CPSM); 8003576: 683b ldr r3, [r7, #0] 8003578: 691b ldr r3, [r3, #16] Command->WaitForInterrupt |\ 800357a: 4313 orrs r3, r2 tmpreg |= (uint32_t)(Command->CmdIndex |\ 800357c: 68fa ldr r2, [r7, #12] 800357e: 4313 orrs r3, r2 8003580: 60fb str r3, [r7, #12] /* Write to SDMMC CMD register */ MODIFY_REG(SDIOx->CMD, CMD_CLEAR_MASK, tmpreg); 8003582: 687b ldr r3, [r7, #4] 8003584: 68db ldr r3, [r3, #12] 8003586: f423 637f bic.w r3, r3, #4080 @ 0xff0 800358a: f023 030f bic.w r3, r3, #15 800358e: 68fa ldr r2, [r7, #12] 8003590: 431a orrs r2, r3 8003592: 687b ldr r3, [r7, #4] 8003594: 60da str r2, [r3, #12] return HAL_OK; 8003596: 2300 movs r3, #0 } 8003598: 4618 mov r0, r3 800359a: 3714 adds r7, #20 800359c: 46bd mov sp, r7 800359e: bc80 pop {r7} 80035a0: 4770 bx lr 080035a2 : * @brief Return the command index of last command for which response received * @param SDIOx: Pointer to SDMMC register base * @retval Command index of the last command response received */ uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx) { 80035a2: b480 push {r7} 80035a4: b083 sub sp, #12 80035a6: af00 add r7, sp, #0 80035a8: 6078 str r0, [r7, #4] return (uint8_t)(SDIOx->RESPCMD); 80035aa: 687b ldr r3, [r7, #4] 80035ac: 691b ldr r3, [r3, #16] 80035ae: b2db uxtb r3, r3 } 80035b0: 4618 mov r0, r3 80035b2: 370c adds r7, #12 80035b4: 46bd mov sp, r7 80035b6: bc80 pop {r7} 80035b8: 4770 bx lr 080035ba : * @arg SDIO_RESP3: Response Register 3 * @arg SDIO_RESP4: Response Register 4 * @retval The Corresponding response register value */ uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response) { 80035ba: b480 push {r7} 80035bc: b085 sub sp, #20 80035be: af00 add r7, sp, #0 80035c0: 6078 str r0, [r7, #4] 80035c2: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_SDIO_RESP(Response)); /* Get the response */ tmp = (uint32_t)(&(SDIOx->RESP1)) + Response; 80035c4: 687b ldr r3, [r7, #4] 80035c6: 3314 adds r3, #20 80035c8: 461a mov r2, r3 80035ca: 683b ldr r3, [r7, #0] 80035cc: 4413 add r3, r2 80035ce: 60fb str r3, [r7, #12] return (*(__IO uint32_t *) tmp); 80035d0: 68fb ldr r3, [r7, #12] 80035d2: 681b ldr r3, [r3, #0] } 80035d4: 4618 mov r0, r3 80035d6: 3714 adds r7, #20 80035d8: 46bd mov sp, r7 80035da: bc80 pop {r7} 80035dc: 4770 bx lr 080035de : * @param Data : pointer to a SDIO_DataInitTypeDef structure * that contains the configuration information for the SDMMC data. * @retval HAL status */ HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data) { 80035de: b480 push {r7} 80035e0: b085 sub sp, #20 80035e2: af00 add r7, sp, #0 80035e4: 6078 str r0, [r7, #4] 80035e6: 6039 str r1, [r7, #0] uint32_t tmpreg = 0; 80035e8: 2300 movs r3, #0 80035ea: 60fb str r3, [r7, #12] assert_param(IS_SDIO_TRANSFER_DIR(Data->TransferDir)); assert_param(IS_SDIO_TRANSFER_MODE(Data->TransferMode)); assert_param(IS_SDIO_DPSM(Data->DPSM)); /* Set the SDMMC Data TimeOut value */ SDIOx->DTIMER = Data->DataTimeOut; 80035ec: 683b ldr r3, [r7, #0] 80035ee: 681a ldr r2, [r3, #0] 80035f0: 687b ldr r3, [r7, #4] 80035f2: 625a str r2, [r3, #36] @ 0x24 /* Set the SDMMC DataLength value */ SDIOx->DLEN = Data->DataLength; 80035f4: 683b ldr r3, [r7, #0] 80035f6: 685a ldr r2, [r3, #4] 80035f8: 687b ldr r3, [r7, #4] 80035fa: 629a str r2, [r3, #40] @ 0x28 /* Set the SDMMC data configuration parameters */ tmpreg |= (uint32_t)(Data->DataBlockSize |\ 80035fc: 683b ldr r3, [r7, #0] 80035fe: 689a ldr r2, [r3, #8] Data->TransferDir |\ 8003600: 683b ldr r3, [r7, #0] 8003602: 68db ldr r3, [r3, #12] tmpreg |= (uint32_t)(Data->DataBlockSize |\ 8003604: 431a orrs r2, r3 Data->TransferMode |\ 8003606: 683b ldr r3, [r7, #0] 8003608: 691b ldr r3, [r3, #16] Data->TransferDir |\ 800360a: 431a orrs r2, r3 Data->DPSM); 800360c: 683b ldr r3, [r7, #0] 800360e: 695b ldr r3, [r3, #20] Data->TransferMode |\ 8003610: 4313 orrs r3, r2 tmpreg |= (uint32_t)(Data->DataBlockSize |\ 8003612: 68fa ldr r2, [r7, #12] 8003614: 4313 orrs r3, r2 8003616: 60fb str r3, [r7, #12] /* Write to SDMMC DCTRL */ MODIFY_REG(SDIOx->DCTRL, DCTRL_CLEAR_MASK, tmpreg); 8003618: 687b ldr r3, [r7, #4] 800361a: 6adb ldr r3, [r3, #44] @ 0x2c 800361c: f023 02f7 bic.w r2, r3, #247 @ 0xf7 8003620: 68fb ldr r3, [r7, #12] 8003622: 431a orrs r2, r3 8003624: 687b ldr r3, [r7, #4] 8003626: 62da str r2, [r3, #44] @ 0x2c return HAL_OK; 8003628: 2300 movs r3, #0 } 800362a: 4618 mov r0, r3 800362c: 3714 adds r7, #20 800362e: 46bd mov sp, r7 8003630: bc80 pop {r7} 8003632: 4770 bx lr 08003634 : * @brief Send the Data Block Length command and check the response * @param SDIOx: Pointer to SDIO register base * @retval HAL status */ uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize) { 8003634: b580 push {r7, lr} 8003636: b088 sub sp, #32 8003638: af00 add r7, sp, #0 800363a: 6078 str r0, [r7, #4] 800363c: 6039 str r1, [r7, #0] SDIO_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)BlockSize; 800363e: 683b ldr r3, [r7, #0] 8003640: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_BLOCKLEN; 8003642: 2310 movs r3, #16 8003644: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; 8003646: 2340 movs r3, #64 @ 0x40 8003648: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; 800364a: 2300 movs r3, #0 800364c: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; 800364e: f44f 6380 mov.w r3, #1024 @ 0x400 8003652: 61bb str r3, [r7, #24] (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); 8003654: f107 0308 add.w r3, r7, #8 8003658: 4619 mov r1, r3 800365a: 6878 ldr r0, [r7, #4] 800365c: f7ff ff78 bl 8003550 /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SET_BLOCKLEN, SDIO_CMDTIMEOUT); 8003660: f241 3288 movw r2, #5000 @ 0x1388 8003664: 2110 movs r1, #16 8003666: 6878 ldr r0, [r7, #4] 8003668: f000 f9d6 bl 8003a18 800366c: 61f8 str r0, [r7, #28] return errorstate; 800366e: 69fb ldr r3, [r7, #28] } 8003670: 4618 mov r0, r3 8003672: 3720 adds r7, #32 8003674: 46bd mov sp, r7 8003676: bd80 pop {r7, pc} 08003678 : * @brief Send the Read Single Block command and check the response * @param SDIOx: Pointer to SDIO register base * @retval HAL status */ uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd) { 8003678: b580 push {r7, lr} 800367a: b088 sub sp, #32 800367c: af00 add r7, sp, #0 800367e: 6078 str r0, [r7, #4] 8003680: 6039 str r1, [r7, #0] SDIO_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)ReadAdd; 8003682: 683b ldr r3, [r7, #0] 8003684: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_SINGLE_BLOCK; 8003686: 2311 movs r3, #17 8003688: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; 800368a: 2340 movs r3, #64 @ 0x40 800368c: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; 800368e: 2300 movs r3, #0 8003690: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; 8003692: f44f 6380 mov.w r3, #1024 @ 0x400 8003696: 61bb str r3, [r7, #24] (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); 8003698: f107 0308 add.w r3, r7, #8 800369c: 4619 mov r1, r3 800369e: 6878 ldr r0, [r7, #4] 80036a0: f7ff ff56 bl 8003550 /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_READ_SINGLE_BLOCK, SDIO_CMDTIMEOUT); 80036a4: f241 3288 movw r2, #5000 @ 0x1388 80036a8: 2111 movs r1, #17 80036aa: 6878 ldr r0, [r7, #4] 80036ac: f000 f9b4 bl 8003a18 80036b0: 61f8 str r0, [r7, #28] return errorstate; 80036b2: 69fb ldr r3, [r7, #28] } 80036b4: 4618 mov r0, r3 80036b6: 3720 adds r7, #32 80036b8: 46bd mov sp, r7 80036ba: bd80 pop {r7, pc} 080036bc : * @brief Send the Read Multi Block command and check the response * @param SDIOx: Pointer to SDIO register base * @retval HAL status */ uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd) { 80036bc: b580 push {r7, lr} 80036be: b088 sub sp, #32 80036c0: af00 add r7, sp, #0 80036c2: 6078 str r0, [r7, #4] 80036c4: 6039 str r1, [r7, #0] SDIO_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)ReadAdd; 80036c6: 683b ldr r3, [r7, #0] 80036c8: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_MULT_BLOCK; 80036ca: 2312 movs r3, #18 80036cc: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; 80036ce: 2340 movs r3, #64 @ 0x40 80036d0: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; 80036d2: 2300 movs r3, #0 80036d4: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; 80036d6: f44f 6380 mov.w r3, #1024 @ 0x400 80036da: 61bb str r3, [r7, #24] (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); 80036dc: f107 0308 add.w r3, r7, #8 80036e0: 4619 mov r1, r3 80036e2: 6878 ldr r0, [r7, #4] 80036e4: f7ff ff34 bl 8003550 /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_READ_MULT_BLOCK, SDIO_CMDTIMEOUT); 80036e8: f241 3288 movw r2, #5000 @ 0x1388 80036ec: 2112 movs r1, #18 80036ee: 6878 ldr r0, [r7, #4] 80036f0: f000 f992 bl 8003a18 80036f4: 61f8 str r0, [r7, #28] return errorstate; 80036f6: 69fb ldr r3, [r7, #28] } 80036f8: 4618 mov r0, r3 80036fa: 3720 adds r7, #32 80036fc: 46bd mov sp, r7 80036fe: bd80 pop {r7, pc} 08003700 : * @brief Send the Write Single Block command and check the response * @param SDIOx: Pointer to SDIO register base * @retval HAL status */ uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd) { 8003700: b580 push {r7, lr} 8003702: b088 sub sp, #32 8003704: af00 add r7, sp, #0 8003706: 6078 str r0, [r7, #4] 8003708: 6039 str r1, [r7, #0] SDIO_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)WriteAdd; 800370a: 683b ldr r3, [r7, #0] 800370c: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_SINGLE_BLOCK; 800370e: 2318 movs r3, #24 8003710: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; 8003712: 2340 movs r3, #64 @ 0x40 8003714: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; 8003716: 2300 movs r3, #0 8003718: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; 800371a: f44f 6380 mov.w r3, #1024 @ 0x400 800371e: 61bb str r3, [r7, #24] (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); 8003720: f107 0308 add.w r3, r7, #8 8003724: 4619 mov r1, r3 8003726: 6878 ldr r0, [r7, #4] 8003728: f7ff ff12 bl 8003550 /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDIO_CMDTIMEOUT); 800372c: f241 3288 movw r2, #5000 @ 0x1388 8003730: 2118 movs r1, #24 8003732: 6878 ldr r0, [r7, #4] 8003734: f000 f970 bl 8003a18 8003738: 61f8 str r0, [r7, #28] return errorstate; 800373a: 69fb ldr r3, [r7, #28] } 800373c: 4618 mov r0, r3 800373e: 3720 adds r7, #32 8003740: 46bd mov sp, r7 8003742: bd80 pop {r7, pc} 08003744 : * @brief Send the Write Multi Block command and check the response * @param SDIOx: Pointer to SDIO register base * @retval HAL status */ uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd) { 8003744: b580 push {r7, lr} 8003746: b088 sub sp, #32 8003748: af00 add r7, sp, #0 800374a: 6078 str r0, [r7, #4] 800374c: 6039 str r1, [r7, #0] SDIO_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)WriteAdd; 800374e: 683b ldr r3, [r7, #0] 8003750: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_MULT_BLOCK; 8003752: 2319 movs r3, #25 8003754: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; 8003756: 2340 movs r3, #64 @ 0x40 8003758: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; 800375a: 2300 movs r3, #0 800375c: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; 800375e: f44f 6380 mov.w r3, #1024 @ 0x400 8003762: 61bb str r3, [r7, #24] (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); 8003764: f107 0308 add.w r3, r7, #8 8003768: 4619 mov r1, r3 800376a: 6878 ldr r0, [r7, #4] 800376c: f7ff fef0 bl 8003550 /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_WRITE_MULT_BLOCK, SDIO_CMDTIMEOUT); 8003770: f241 3288 movw r2, #5000 @ 0x1388 8003774: 2119 movs r1, #25 8003776: 6878 ldr r0, [r7, #4] 8003778: f000 f94e bl 8003a18 800377c: 61f8 str r0, [r7, #28] return errorstate; 800377e: 69fb ldr r3, [r7, #28] } 8003780: 4618 mov r0, r3 8003782: 3720 adds r7, #32 8003784: 46bd mov sp, r7 8003786: bd80 pop {r7, pc} 08003788 : * @brief Send the Stop Transfer command and check the response. * @param SDIOx: Pointer to SDIO register base * @retval HAL status */ uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx) { 8003788: b580 push {r7, lr} 800378a: b088 sub sp, #32 800378c: af00 add r7, sp, #0 800378e: 6078 str r0, [r7, #4] SDIO_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; /* Send CMD12 STOP_TRANSMISSION */ sdmmc_cmdinit.Argument = 0U; 8003790: 2300 movs r3, #0 8003792: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_STOP_TRANSMISSION; 8003794: 230c movs r3, #12 8003796: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; 8003798: 2340 movs r3, #64 @ 0x40 800379a: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; 800379c: 2300 movs r3, #0 800379e: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; 80037a0: f44f 6380 mov.w r3, #1024 @ 0x400 80037a4: 61bb str r3, [r7, #24] (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); 80037a6: f107 0308 add.w r3, r7, #8 80037aa: 4619 mov r1, r3 80037ac: 6878 ldr r0, [r7, #4] 80037ae: f7ff fecf bl 8003550 /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_STOP_TRANSMISSION, SDIO_STOPTRANSFERTIMEOUT); 80037b2: 4a05 ldr r2, [pc, #20] @ (80037c8 ) 80037b4: 210c movs r1, #12 80037b6: 6878 ldr r0, [r7, #4] 80037b8: f000 f92e bl 8003a18 80037bc: 61f8 str r0, [r7, #28] return errorstate; 80037be: 69fb ldr r3, [r7, #28] } 80037c0: 4618 mov r0, r3 80037c2: 3720 adds r7, #32 80037c4: 46bd mov sp, r7 80037c6: bd80 pop {r7, pc} 80037c8: 05f5e100 .word 0x05f5e100 080037cc : * @param SDIOx: Pointer to SDIO register base * @param addr: Address of the card to be selected * @retval HAL status */ uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr) { 80037cc: b580 push {r7, lr} 80037ce: b08a sub sp, #40 @ 0x28 80037d0: af00 add r7, sp, #0 80037d2: 60f8 str r0, [r7, #12] 80037d4: e9c7 2300 strd r2, r3, [r7] SDIO_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; /* Send CMD7 SDMMC_SEL_DESEL_CARD */ sdmmc_cmdinit.Argument = (uint32_t)Addr; 80037d8: 683b ldr r3, [r7, #0] 80037da: 613b str r3, [r7, #16] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEL_DESEL_CARD; 80037dc: 2307 movs r3, #7 80037de: 617b str r3, [r7, #20] sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; 80037e0: 2340 movs r3, #64 @ 0x40 80037e2: 61bb str r3, [r7, #24] sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; 80037e4: 2300 movs r3, #0 80037e6: 61fb str r3, [r7, #28] sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; 80037e8: f44f 6380 mov.w r3, #1024 @ 0x400 80037ec: 623b str r3, [r7, #32] (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); 80037ee: f107 0310 add.w r3, r7, #16 80037f2: 4619 mov r1, r3 80037f4: 68f8 ldr r0, [r7, #12] 80037f6: f7ff feab bl 8003550 /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SEL_DESEL_CARD, SDIO_CMDTIMEOUT); 80037fa: f241 3288 movw r2, #5000 @ 0x1388 80037fe: 2107 movs r1, #7 8003800: 68f8 ldr r0, [r7, #12] 8003802: f000 f909 bl 8003a18 8003806: 6278 str r0, [r7, #36] @ 0x24 return errorstate; 8003808: 6a7b ldr r3, [r7, #36] @ 0x24 } 800380a: 4618 mov r0, r3 800380c: 3728 adds r7, #40 @ 0x28 800380e: 46bd mov sp, r7 8003810: bd80 pop {r7, pc} 08003812 : * @brief Send the Go Idle State command and check the response. * @param SDIOx: Pointer to SDIO register base * @retval HAL status */ uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx) { 8003812: b580 push {r7, lr} 8003814: b088 sub sp, #32 8003816: af00 add r7, sp, #0 8003818: 6078 str r0, [r7, #4] SDIO_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; sdmmc_cmdinit.Argument = 0U; 800381a: 2300 movs r3, #0 800381c: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_GO_IDLE_STATE; 800381e: 2300 movs r3, #0 8003820: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDIO_RESPONSE_NO; 8003822: 2300 movs r3, #0 8003824: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; 8003826: 2300 movs r3, #0 8003828: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; 800382a: f44f 6380 mov.w r3, #1024 @ 0x400 800382e: 61bb str r3, [r7, #24] (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); 8003830: f107 0308 add.w r3, r7, #8 8003834: 4619 mov r1, r3 8003836: 6878 ldr r0, [r7, #4] 8003838: f7ff fe8a bl 8003550 /* Check for error conditions */ errorstate = SDMMC_GetCmdError(SDIOx); 800383c: 6878 ldr r0, [r7, #4] 800383e: f000 fb21 bl 8003e84 8003842: 61f8 str r0, [r7, #28] return errorstate; 8003844: 69fb ldr r3, [r7, #28] } 8003846: 4618 mov r0, r3 8003848: 3720 adds r7, #32 800384a: 46bd mov sp, r7 800384c: bd80 pop {r7, pc} 0800384e : * @brief Send the Operating Condition command and check the response. * @param SDIOx: Pointer to SDIO register base * @retval HAL status */ uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx) { 800384e: b580 push {r7, lr} 8003850: b088 sub sp, #32 8003852: af00 add r7, sp, #0 8003854: 6078 str r0, [r7, #4] /* Send CMD8 to verify SD card interface operating condition */ /* Argument: - [31:12]: Reserved (shall be set to '0') - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V) - [7:0]: Check Pattern (recommended 0xAA) */ /* CMD Response: R7 */ sdmmc_cmdinit.Argument = SDMMC_CHECK_PATTERN; 8003856: f44f 73d5 mov.w r3, #426 @ 0x1aa 800385a: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD; 800385c: 2308 movs r3, #8 800385e: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; 8003860: 2340 movs r3, #64 @ 0x40 8003862: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; 8003864: 2300 movs r3, #0 8003866: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; 8003868: f44f 6380 mov.w r3, #1024 @ 0x400 800386c: 61bb str r3, [r7, #24] (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); 800386e: f107 0308 add.w r3, r7, #8 8003872: 4619 mov r1, r3 8003874: 6878 ldr r0, [r7, #4] 8003876: f7ff fe6b bl 8003550 /* Check for error conditions */ errorstate = SDMMC_GetCmdResp7(SDIOx); 800387a: 6878 ldr r0, [r7, #4] 800387c: f000 fab4 bl 8003de8 8003880: 61f8 str r0, [r7, #28] return errorstate; 8003882: 69fb ldr r3, [r7, #28] } 8003884: 4618 mov r0, r3 8003886: 3720 adds r7, #32 8003888: 46bd mov sp, r7 800388a: bd80 pop {r7, pc} 0800388c : * @param SDIOx: Pointer to SDIO register base * @param Argument: Command Argument * @retval HAL status */ uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument) { 800388c: b580 push {r7, lr} 800388e: b088 sub sp, #32 8003890: af00 add r7, sp, #0 8003892: 6078 str r0, [r7, #4] 8003894: 6039 str r1, [r7, #0] SDIO_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; sdmmc_cmdinit.Argument = (uint32_t)Argument; 8003896: 683b ldr r3, [r7, #0] 8003898: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_CMD; 800389a: 2337 movs r3, #55 @ 0x37 800389c: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; 800389e: 2340 movs r3, #64 @ 0x40 80038a0: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; 80038a2: 2300 movs r3, #0 80038a4: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; 80038a6: f44f 6380 mov.w r3, #1024 @ 0x400 80038aa: 61bb str r3, [r7, #24] (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); 80038ac: f107 0308 add.w r3, r7, #8 80038b0: 4619 mov r1, r3 80038b2: 6878 ldr r0, [r7, #4] 80038b4: f7ff fe4c bl 8003550 /* Check for error conditions */ /* If there is a HAL_ERROR, it is a MMC card, else it is a SD card: SD card 2.0 (voltage range mismatch) or SD card 1.x */ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_APP_CMD, SDIO_CMDTIMEOUT); 80038b8: f241 3288 movw r2, #5000 @ 0x1388 80038bc: 2137 movs r1, #55 @ 0x37 80038be: 6878 ldr r0, [r7, #4] 80038c0: f000 f8aa bl 8003a18 80038c4: 61f8 str r0, [r7, #28] return errorstate; 80038c6: 69fb ldr r3, [r7, #28] } 80038c8: 4618 mov r0, r3 80038ca: 3720 adds r7, #32 80038cc: 46bd mov sp, r7 80038ce: bd80 pop {r7, pc} 080038d0 : * @param SDIOx: Pointer to SDIO register base * @param Argument: Command Argument * @retval HAL status */ uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t Argument) { 80038d0: b580 push {r7, lr} 80038d2: b088 sub sp, #32 80038d4: af00 add r7, sp, #0 80038d6: 6078 str r0, [r7, #4] 80038d8: 6039 str r1, [r7, #0] SDIO_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; sdmmc_cmdinit.Argument = SDMMC_VOLTAGE_WINDOW_SD | Argument; 80038da: 683b ldr r3, [r7, #0] 80038dc: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 80038e0: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 80038e4: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_OP_COND; 80038e6: 2329 movs r3, #41 @ 0x29 80038e8: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; 80038ea: 2340 movs r3, #64 @ 0x40 80038ec: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; 80038ee: 2300 movs r3, #0 80038f0: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; 80038f2: f44f 6380 mov.w r3, #1024 @ 0x400 80038f6: 61bb str r3, [r7, #24] (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); 80038f8: f107 0308 add.w r3, r7, #8 80038fc: 4619 mov r1, r3 80038fe: 6878 ldr r0, [r7, #4] 8003900: f7ff fe26 bl 8003550 /* Check for error conditions */ errorstate = SDMMC_GetCmdResp3(SDIOx); 8003904: 6878 ldr r0, [r7, #4] 8003906: f000 f9bd bl 8003c84 800390a: 61f8 str r0, [r7, #28] return errorstate; 800390c: 69fb ldr r3, [r7, #28] } 800390e: 4618 mov r0, r3 8003910: 3720 adds r7, #32 8003912: 46bd mov sp, r7 8003914: bd80 pop {r7, pc} 08003916 : * @brief Send the Send CID command and check the response. * @param SDIOx: Pointer to SDIO register base * @retval HAL status */ uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx) { 8003916: b580 push {r7, lr} 8003918: b088 sub sp, #32 800391a: af00 add r7, sp, #0 800391c: 6078 str r0, [r7, #4] SDIO_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; /* Send CMD2 ALL_SEND_CID */ sdmmc_cmdinit.Argument = 0U; 800391e: 2300 movs r3, #0 8003920: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ALL_SEND_CID; 8003922: 2302 movs r3, #2 8003924: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDIO_RESPONSE_LONG; 8003926: 23c0 movs r3, #192 @ 0xc0 8003928: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; 800392a: 2300 movs r3, #0 800392c: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; 800392e: f44f 6380 mov.w r3, #1024 @ 0x400 8003932: 61bb str r3, [r7, #24] (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); 8003934: f107 0308 add.w r3, r7, #8 8003938: 4619 mov r1, r3 800393a: 6878 ldr r0, [r7, #4] 800393c: f7ff fe08 bl 8003550 /* Check for error conditions */ errorstate = SDMMC_GetCmdResp2(SDIOx); 8003940: 6878 ldr r0, [r7, #4] 8003942: f000 f957 bl 8003bf4 8003946: 61f8 str r0, [r7, #28] return errorstate; 8003948: 69fb ldr r3, [r7, #28] } 800394a: 4618 mov r0, r3 800394c: 3720 adds r7, #32 800394e: 46bd mov sp, r7 8003950: bd80 pop {r7, pc} 08003952 : * @param SDIOx: Pointer to SDIO register base * @param Argument: Command Argument * @retval HAL status */ uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument) { 8003952: b580 push {r7, lr} 8003954: b088 sub sp, #32 8003956: af00 add r7, sp, #0 8003958: 6078 str r0, [r7, #4] 800395a: 6039 str r1, [r7, #0] SDIO_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; /* Send CMD9 SEND_CSD */ sdmmc_cmdinit.Argument = Argument; 800395c: 683b ldr r3, [r7, #0] 800395e: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_CSD; 8003960: 2309 movs r3, #9 8003962: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDIO_RESPONSE_LONG; 8003964: 23c0 movs r3, #192 @ 0xc0 8003966: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; 8003968: 2300 movs r3, #0 800396a: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; 800396c: f44f 6380 mov.w r3, #1024 @ 0x400 8003970: 61bb str r3, [r7, #24] (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); 8003972: f107 0308 add.w r3, r7, #8 8003976: 4619 mov r1, r3 8003978: 6878 ldr r0, [r7, #4] 800397a: f7ff fde9 bl 8003550 /* Check for error conditions */ errorstate = SDMMC_GetCmdResp2(SDIOx); 800397e: 6878 ldr r0, [r7, #4] 8003980: f000 f938 bl 8003bf4 8003984: 61f8 str r0, [r7, #28] return errorstate; 8003986: 69fb ldr r3, [r7, #28] } 8003988: 4618 mov r0, r3 800398a: 3720 adds r7, #32 800398c: 46bd mov sp, r7 800398e: bd80 pop {r7, pc} 08003990 : * @param SDIOx: Pointer to SDIO register base * @param pRCA: Card RCA * @retval HAL status */ uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA) { 8003990: b580 push {r7, lr} 8003992: b088 sub sp, #32 8003994: af00 add r7, sp, #0 8003996: 6078 str r0, [r7, #4] 8003998: 6039 str r1, [r7, #0] SDIO_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; /* Send CMD3 SD_CMD_SET_REL_ADDR */ sdmmc_cmdinit.Argument = 0U; 800399a: 2300 movs r3, #0 800399c: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR; 800399e: 2303 movs r3, #3 80039a0: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; 80039a2: 2340 movs r3, #64 @ 0x40 80039a4: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; 80039a6: 2300 movs r3, #0 80039a8: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; 80039aa: f44f 6380 mov.w r3, #1024 @ 0x400 80039ae: 61bb str r3, [r7, #24] (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); 80039b0: f107 0308 add.w r3, r7, #8 80039b4: 4619 mov r1, r3 80039b6: 6878 ldr r0, [r7, #4] 80039b8: f7ff fdca bl 8003550 /* Check for error conditions */ errorstate = SDMMC_GetCmdResp6(SDIOx, SDMMC_CMD_SET_REL_ADDR, pRCA); 80039bc: 683a ldr r2, [r7, #0] 80039be: 2103 movs r1, #3 80039c0: 6878 ldr r0, [r7, #4] 80039c2: f000 f99b bl 8003cfc 80039c6: 61f8 str r0, [r7, #28] return errorstate; 80039c8: 69fb ldr r3, [r7, #28] } 80039ca: 4618 mov r0, r3 80039cc: 3720 adds r7, #32 80039ce: 46bd mov sp, r7 80039d0: bd80 pop {r7, pc} 080039d2 : * @param SDIOx: Pointer to SDIO register base * @param Argument: Command Argument * @retval HAL status */ uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument) { 80039d2: b580 push {r7, lr} 80039d4: b088 sub sp, #32 80039d6: af00 add r7, sp, #0 80039d8: 6078 str r0, [r7, #4] 80039da: 6039 str r1, [r7, #0] SDIO_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; sdmmc_cmdinit.Argument = Argument; 80039dc: 683b ldr r3, [r7, #0] 80039de: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_STATUS; 80039e0: 230d movs r3, #13 80039e2: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; 80039e4: 2340 movs r3, #64 @ 0x40 80039e6: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; 80039e8: 2300 movs r3, #0 80039ea: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; 80039ec: f44f 6380 mov.w r3, #1024 @ 0x400 80039f0: 61bb str r3, [r7, #24] (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); 80039f2: f107 0308 add.w r3, r7, #8 80039f6: 4619 mov r1, r3 80039f8: 6878 ldr r0, [r7, #4] 80039fa: f7ff fda9 bl 8003550 /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SEND_STATUS, SDIO_CMDTIMEOUT); 80039fe: f241 3288 movw r2, #5000 @ 0x1388 8003a02: 210d movs r1, #13 8003a04: 6878 ldr r0, [r7, #4] 8003a06: f000 f807 bl 8003a18 8003a0a: 61f8 str r0, [r7, #28] return errorstate; 8003a0c: 69fb ldr r3, [r7, #28] } 8003a0e: 4618 mov r0, r3 8003a10: 3720 adds r7, #32 8003a12: 46bd mov sp, r7 8003a14: bd80 pop {r7, pc} ... 08003a18 : * @param SDIOx Pointer to SDMMC register base * @param SD_CMD: The sent command index * @retval SD Card error state */ uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout) { 8003a18: b580 push {r7, lr} 8003a1a: b088 sub sp, #32 8003a1c: af00 add r7, sp, #0 8003a1e: 60f8 str r0, [r7, #12] 8003a20: 460b mov r3, r1 8003a22: 607a str r2, [r7, #4] 8003a24: 72fb strb r3, [r7, #11] uint32_t response_r1; uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. The Timeout is expressed in ms */ uint32_t count = Timeout * (SystemCoreClock / 8U /1000U); 8003a26: 4b70 ldr r3, [pc, #448] @ (8003be8 ) 8003a28: 681b ldr r3, [r3, #0] 8003a2a: 4a70 ldr r2, [pc, #448] @ (8003bec ) 8003a2c: fba2 2303 umull r2, r3, r2, r3 8003a30: 0a5a lsrs r2, r3, #9 8003a32: 687b ldr r3, [r7, #4] 8003a34: fb02 f303 mul.w r3, r2, r3 8003a38: 61fb str r3, [r7, #28] do { if (count-- == 0U) 8003a3a: 69fb ldr r3, [r7, #28] 8003a3c: 1e5a subs r2, r3, #1 8003a3e: 61fa str r2, [r7, #28] 8003a40: 2b00 cmp r3, #0 8003a42: d102 bne.n 8003a4a { return SDMMC_ERROR_TIMEOUT; 8003a44: f04f 4300 mov.w r3, #2147483648 @ 0x80000000 8003a48: e0c9 b.n 8003bde } sta_reg = SDIOx->STA; 8003a4a: 68fb ldr r3, [r7, #12] 8003a4c: 6b5b ldr r3, [r3, #52] @ 0x34 8003a4e: 61bb str r3, [r7, #24] }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) || 8003a50: 69bb ldr r3, [r7, #24] 8003a52: f003 0345 and.w r3, r3, #69 @ 0x45 8003a56: 2b00 cmp r3, #0 8003a58: d0ef beq.n 8003a3a ((sta_reg & SDIO_FLAG_CMDACT) != 0U )); 8003a5a: 69bb ldr r3, [r7, #24] 8003a5c: f403 6300 and.w r3, r3, #2048 @ 0x800 }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) || 8003a60: 2b00 cmp r3, #0 8003a62: d1ea bne.n 8003a3a if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT)) 8003a64: 68fb ldr r3, [r7, #12] 8003a66: 6b5b ldr r3, [r3, #52] @ 0x34 8003a68: f003 0304 and.w r3, r3, #4 8003a6c: 2b00 cmp r3, #0 8003a6e: d004 beq.n 8003a7a { __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT); 8003a70: 68fb ldr r3, [r7, #12] 8003a72: 2204 movs r2, #4 8003a74: 639a str r2, [r3, #56] @ 0x38 return SDMMC_ERROR_CMD_RSP_TIMEOUT; 8003a76: 2304 movs r3, #4 8003a78: e0b1 b.n 8003bde } else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL)) 8003a7a: 68fb ldr r3, [r7, #12] 8003a7c: 6b5b ldr r3, [r3, #52] @ 0x34 8003a7e: f003 0301 and.w r3, r3, #1 8003a82: 2b00 cmp r3, #0 8003a84: d004 beq.n 8003a90 { __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL); 8003a86: 68fb ldr r3, [r7, #12] 8003a88: 2201 movs r2, #1 8003a8a: 639a str r2, [r3, #56] @ 0x38 return SDMMC_ERROR_CMD_CRC_FAIL; 8003a8c: 2301 movs r3, #1 8003a8e: e0a6 b.n 8003bde { /* Nothing to do */ } /* Clear all the static flags */ __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS); 8003a90: 68fb ldr r3, [r7, #12] 8003a92: 22c5 movs r2, #197 @ 0xc5 8003a94: 639a str r2, [r3, #56] @ 0x38 /* Check response received is of desired command */ if(SDIO_GetCommandResponse(SDIOx) != SD_CMD) 8003a96: 68f8 ldr r0, [r7, #12] 8003a98: f7ff fd83 bl 80035a2 8003a9c: 4603 mov r3, r0 8003a9e: 461a mov r2, r3 8003aa0: 7afb ldrb r3, [r7, #11] 8003aa2: 4293 cmp r3, r2 8003aa4: d001 beq.n 8003aaa { return SDMMC_ERROR_CMD_CRC_FAIL; 8003aa6: 2301 movs r3, #1 8003aa8: e099 b.n 8003bde } /* We have received response, retrieve it for analysis */ response_r1 = SDIO_GetResponse(SDIOx, SDIO_RESP1); 8003aaa: 2100 movs r1, #0 8003aac: 68f8 ldr r0, [r7, #12] 8003aae: f7ff fd84 bl 80035ba 8003ab2: 6178 str r0, [r7, #20] if((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO) 8003ab4: 697a ldr r2, [r7, #20] 8003ab6: 4b4e ldr r3, [pc, #312] @ (8003bf0 ) 8003ab8: 4013 ands r3, r2 8003aba: 2b00 cmp r3, #0 8003abc: d101 bne.n 8003ac2 { return SDMMC_ERROR_NONE; 8003abe: 2300 movs r3, #0 8003ac0: e08d b.n 8003bde } else if((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE) 8003ac2: 697b ldr r3, [r7, #20] 8003ac4: 2b00 cmp r3, #0 8003ac6: da02 bge.n 8003ace { return SDMMC_ERROR_ADDR_OUT_OF_RANGE; 8003ac8: f04f 7300 mov.w r3, #33554432 @ 0x2000000 8003acc: e087 b.n 8003bde } else if((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED) 8003ace: 697b ldr r3, [r7, #20] 8003ad0: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000 8003ad4: 2b00 cmp r3, #0 8003ad6: d001 beq.n 8003adc { return SDMMC_ERROR_ADDR_MISALIGNED; 8003ad8: 2340 movs r3, #64 @ 0x40 8003ada: e080 b.n 8003bde } else if((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR) 8003adc: 697b ldr r3, [r7, #20] 8003ade: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8003ae2: 2b00 cmp r3, #0 8003ae4: d001 beq.n 8003aea { return SDMMC_ERROR_BLOCK_LEN_ERR; 8003ae6: 2380 movs r3, #128 @ 0x80 8003ae8: e079 b.n 8003bde } else if((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR) 8003aea: 697b ldr r3, [r7, #20] 8003aec: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8003af0: 2b00 cmp r3, #0 8003af2: d002 beq.n 8003afa { return SDMMC_ERROR_ERASE_SEQ_ERR; 8003af4: f44f 7380 mov.w r3, #256 @ 0x100 8003af8: e071 b.n 8003bde } else if((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM) 8003afa: 697b ldr r3, [r7, #20] 8003afc: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8003b00: 2b00 cmp r3, #0 8003b02: d002 beq.n 8003b0a { return SDMMC_ERROR_BAD_ERASE_PARAM; 8003b04: f44f 7300 mov.w r3, #512 @ 0x200 8003b08: e069 b.n 8003bde } else if((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION) 8003b0a: 697b ldr r3, [r7, #20] 8003b0c: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 8003b10: 2b00 cmp r3, #0 8003b12: d002 beq.n 8003b1a { return SDMMC_ERROR_WRITE_PROT_VIOLATION; 8003b14: f44f 6380 mov.w r3, #1024 @ 0x400 8003b18: e061 b.n 8003bde } else if((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED) 8003b1a: 697b ldr r3, [r7, #20] 8003b1c: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8003b20: 2b00 cmp r3, #0 8003b22: d002 beq.n 8003b2a { return SDMMC_ERROR_LOCK_UNLOCK_FAILED; 8003b24: f44f 6300 mov.w r3, #2048 @ 0x800 8003b28: e059 b.n 8003bde } else if((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED) 8003b2a: 697b ldr r3, [r7, #20] 8003b2c: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8003b30: 2b00 cmp r3, #0 8003b32: d002 beq.n 8003b3a { return SDMMC_ERROR_COM_CRC_FAILED; 8003b34: f44f 5380 mov.w r3, #4096 @ 0x1000 8003b38: e051 b.n 8003bde } else if((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD) 8003b3a: 697b ldr r3, [r7, #20] 8003b3c: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8003b40: 2b00 cmp r3, #0 8003b42: d002 beq.n 8003b4a { return SDMMC_ERROR_ILLEGAL_CMD; 8003b44: f44f 5300 mov.w r3, #8192 @ 0x2000 8003b48: e049 b.n 8003bde } else if((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED) 8003b4a: 697b ldr r3, [r7, #20] 8003b4c: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8003b50: 2b00 cmp r3, #0 8003b52: d002 beq.n 8003b5a { return SDMMC_ERROR_CARD_ECC_FAILED; 8003b54: f44f 4380 mov.w r3, #16384 @ 0x4000 8003b58: e041 b.n 8003bde } else if((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR) 8003b5a: 697b ldr r3, [r7, #20] 8003b5c: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8003b60: 2b00 cmp r3, #0 8003b62: d002 beq.n 8003b6a { return SDMMC_ERROR_CC_ERR; 8003b64: f44f 4300 mov.w r3, #32768 @ 0x8000 8003b68: e039 b.n 8003bde } else if((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN) 8003b6a: 697b ldr r3, [r7, #20] 8003b6c: f403 2380 and.w r3, r3, #262144 @ 0x40000 8003b70: 2b00 cmp r3, #0 8003b72: d002 beq.n 8003b7a { return SDMMC_ERROR_STREAM_READ_UNDERRUN; 8003b74: f44f 3300 mov.w r3, #131072 @ 0x20000 8003b78: e031 b.n 8003bde } else if((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN) 8003b7a: 697b ldr r3, [r7, #20] 8003b7c: f403 3300 and.w r3, r3, #131072 @ 0x20000 8003b80: 2b00 cmp r3, #0 8003b82: d002 beq.n 8003b8a { return SDMMC_ERROR_STREAM_WRITE_OVERRUN; 8003b84: f44f 2380 mov.w r3, #262144 @ 0x40000 8003b88: e029 b.n 8003bde } else if((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE) 8003b8a: 697b ldr r3, [r7, #20] 8003b8c: f403 3380 and.w r3, r3, #65536 @ 0x10000 8003b90: 2b00 cmp r3, #0 8003b92: d002 beq.n 8003b9a { return SDMMC_ERROR_CID_CSD_OVERWRITE; 8003b94: f44f 2300 mov.w r3, #524288 @ 0x80000 8003b98: e021 b.n 8003bde } else if((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP) 8003b9a: 697b ldr r3, [r7, #20] 8003b9c: f403 4300 and.w r3, r3, #32768 @ 0x8000 8003ba0: 2b00 cmp r3, #0 8003ba2: d002 beq.n 8003baa { return SDMMC_ERROR_WP_ERASE_SKIP; 8003ba4: f44f 1380 mov.w r3, #1048576 @ 0x100000 8003ba8: e019 b.n 8003bde } else if((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED) 8003baa: 697b ldr r3, [r7, #20] 8003bac: f403 4380 and.w r3, r3, #16384 @ 0x4000 8003bb0: 2b00 cmp r3, #0 8003bb2: d002 beq.n 8003bba { return SDMMC_ERROR_CARD_ECC_DISABLED; 8003bb4: f44f 1300 mov.w r3, #2097152 @ 0x200000 8003bb8: e011 b.n 8003bde } else if((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET) 8003bba: 697b ldr r3, [r7, #20] 8003bbc: f403 5300 and.w r3, r3, #8192 @ 0x2000 8003bc0: 2b00 cmp r3, #0 8003bc2: d002 beq.n 8003bca { return SDMMC_ERROR_ERASE_RESET; 8003bc4: f44f 0380 mov.w r3, #4194304 @ 0x400000 8003bc8: e009 b.n 8003bde } else if((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR) 8003bca: 697b ldr r3, [r7, #20] 8003bcc: f003 0308 and.w r3, r3, #8 8003bd0: 2b00 cmp r3, #0 8003bd2: d002 beq.n 8003bda { return SDMMC_ERROR_AKE_SEQ_ERR; 8003bd4: f44f 0300 mov.w r3, #8388608 @ 0x800000 8003bd8: e001 b.n 8003bde } else { return SDMMC_ERROR_GENERAL_UNKNOWN_ERR; 8003bda: f44f 3380 mov.w r3, #65536 @ 0x10000 } } 8003bde: 4618 mov r0, r3 8003be0: 3720 adds r7, #32 8003be2: 46bd mov sp, r7 8003be4: bd80 pop {r7, pc} 8003be6: bf00 nop 8003be8: 20000000 .word 0x20000000 8003bec: 10624dd3 .word 0x10624dd3 8003bf0: fdffe008 .word 0xfdffe008 08003bf4 : * @brief Checks for error conditions for R2 (CID or CSD) response. * @param SDIOx Pointer to SDMMC register base * @retval SD Card error state */ uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx) { 8003bf4: b480 push {r7} 8003bf6: b085 sub sp, #20 8003bf8: af00 add r7, sp, #0 8003bfa: 6078 str r0, [r7, #4] uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. The SDIO_CMDTIMEOUT is expressed in ms */ uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); 8003bfc: 4b1f ldr r3, [pc, #124] @ (8003c7c ) 8003bfe: 681b ldr r3, [r3, #0] 8003c00: 4a1f ldr r2, [pc, #124] @ (8003c80 ) 8003c02: fba2 2303 umull r2, r3, r2, r3 8003c06: 0a5b lsrs r3, r3, #9 8003c08: f241 3288 movw r2, #5000 @ 0x1388 8003c0c: fb02 f303 mul.w r3, r2, r3 8003c10: 60fb str r3, [r7, #12] do { if (count-- == 0U) 8003c12: 68fb ldr r3, [r7, #12] 8003c14: 1e5a subs r2, r3, #1 8003c16: 60fa str r2, [r7, #12] 8003c18: 2b00 cmp r3, #0 8003c1a: d102 bne.n 8003c22 { return SDMMC_ERROR_TIMEOUT; 8003c1c: f04f 4300 mov.w r3, #2147483648 @ 0x80000000 8003c20: e026 b.n 8003c70 } sta_reg = SDIOx->STA; 8003c22: 687b ldr r3, [r7, #4] 8003c24: 6b5b ldr r3, [r3, #52] @ 0x34 8003c26: 60bb str r3, [r7, #8] }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) || 8003c28: 68bb ldr r3, [r7, #8] 8003c2a: f003 0345 and.w r3, r3, #69 @ 0x45 8003c2e: 2b00 cmp r3, #0 8003c30: d0ef beq.n 8003c12 ((sta_reg & SDIO_FLAG_CMDACT) != 0U )); 8003c32: 68bb ldr r3, [r7, #8] 8003c34: f403 6300 and.w r3, r3, #2048 @ 0x800 }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) || 8003c38: 2b00 cmp r3, #0 8003c3a: d1ea bne.n 8003c12 if (__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT)) 8003c3c: 687b ldr r3, [r7, #4] 8003c3e: 6b5b ldr r3, [r3, #52] @ 0x34 8003c40: f003 0304 and.w r3, r3, #4 8003c44: 2b00 cmp r3, #0 8003c46: d004 beq.n 8003c52 { __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT); 8003c48: 687b ldr r3, [r7, #4] 8003c4a: 2204 movs r2, #4 8003c4c: 639a str r2, [r3, #56] @ 0x38 return SDMMC_ERROR_CMD_RSP_TIMEOUT; 8003c4e: 2304 movs r3, #4 8003c50: e00e b.n 8003c70 } else if (__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL)) 8003c52: 687b ldr r3, [r7, #4] 8003c54: 6b5b ldr r3, [r3, #52] @ 0x34 8003c56: f003 0301 and.w r3, r3, #1 8003c5a: 2b00 cmp r3, #0 8003c5c: d004 beq.n 8003c68 { __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL); 8003c5e: 687b ldr r3, [r7, #4] 8003c60: 2201 movs r2, #1 8003c62: 639a str r2, [r3, #56] @ 0x38 return SDMMC_ERROR_CMD_CRC_FAIL; 8003c64: 2301 movs r3, #1 8003c66: e003 b.n 8003c70 } else { /* No error flag set */ /* Clear all the static flags */ __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS); 8003c68: 687b ldr r3, [r7, #4] 8003c6a: 22c5 movs r2, #197 @ 0xc5 8003c6c: 639a str r2, [r3, #56] @ 0x38 } return SDMMC_ERROR_NONE; 8003c6e: 2300 movs r3, #0 } 8003c70: 4618 mov r0, r3 8003c72: 3714 adds r7, #20 8003c74: 46bd mov sp, r7 8003c76: bc80 pop {r7} 8003c78: 4770 bx lr 8003c7a: bf00 nop 8003c7c: 20000000 .word 0x20000000 8003c80: 10624dd3 .word 0x10624dd3 08003c84 : * @brief Checks for error conditions for R3 (OCR) response. * @param SDIOx Pointer to SDMMC register base * @retval SD Card error state */ uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx) { 8003c84: b480 push {r7} 8003c86: b085 sub sp, #20 8003c88: af00 add r7, sp, #0 8003c8a: 6078 str r0, [r7, #4] uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. The SDIO_CMDTIMEOUT is expressed in ms */ uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); 8003c8c: 4b19 ldr r3, [pc, #100] @ (8003cf4 ) 8003c8e: 681b ldr r3, [r3, #0] 8003c90: 4a19 ldr r2, [pc, #100] @ (8003cf8 ) 8003c92: fba2 2303 umull r2, r3, r2, r3 8003c96: 0a5b lsrs r3, r3, #9 8003c98: f241 3288 movw r2, #5000 @ 0x1388 8003c9c: fb02 f303 mul.w r3, r2, r3 8003ca0: 60fb str r3, [r7, #12] do { if (count-- == 0U) 8003ca2: 68fb ldr r3, [r7, #12] 8003ca4: 1e5a subs r2, r3, #1 8003ca6: 60fa str r2, [r7, #12] 8003ca8: 2b00 cmp r3, #0 8003caa: d102 bne.n 8003cb2 { return SDMMC_ERROR_TIMEOUT; 8003cac: f04f 4300 mov.w r3, #2147483648 @ 0x80000000 8003cb0: e01b b.n 8003cea } sta_reg = SDIOx->STA; 8003cb2: 687b ldr r3, [r7, #4] 8003cb4: 6b5b ldr r3, [r3, #52] @ 0x34 8003cb6: 60bb str r3, [r7, #8] }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) || 8003cb8: 68bb ldr r3, [r7, #8] 8003cba: f003 0345 and.w r3, r3, #69 @ 0x45 8003cbe: 2b00 cmp r3, #0 8003cc0: d0ef beq.n 8003ca2 ((sta_reg & SDIO_FLAG_CMDACT) != 0U )); 8003cc2: 68bb ldr r3, [r7, #8] 8003cc4: f403 6300 and.w r3, r3, #2048 @ 0x800 }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) || 8003cc8: 2b00 cmp r3, #0 8003cca: d1ea bne.n 8003ca2 if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT)) 8003ccc: 687b ldr r3, [r7, #4] 8003cce: 6b5b ldr r3, [r3, #52] @ 0x34 8003cd0: f003 0304 and.w r3, r3, #4 8003cd4: 2b00 cmp r3, #0 8003cd6: d004 beq.n 8003ce2 { __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT); 8003cd8: 687b ldr r3, [r7, #4] 8003cda: 2204 movs r2, #4 8003cdc: 639a str r2, [r3, #56] @ 0x38 return SDMMC_ERROR_CMD_RSP_TIMEOUT; 8003cde: 2304 movs r3, #4 8003ce0: e003 b.n 8003cea } else { /* Clear all the static flags */ __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS); 8003ce2: 687b ldr r3, [r7, #4] 8003ce4: 22c5 movs r2, #197 @ 0xc5 8003ce6: 639a str r2, [r3, #56] @ 0x38 } return SDMMC_ERROR_NONE; 8003ce8: 2300 movs r3, #0 } 8003cea: 4618 mov r0, r3 8003cec: 3714 adds r7, #20 8003cee: 46bd mov sp, r7 8003cf0: bc80 pop {r7} 8003cf2: 4770 bx lr 8003cf4: 20000000 .word 0x20000000 8003cf8: 10624dd3 .word 0x10624dd3 08003cfc : * @param pRCA: Pointer to the variable that will contain the SD card relative * address RCA * @retval SD Card error state */ uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA) { 8003cfc: b580 push {r7, lr} 8003cfe: b088 sub sp, #32 8003d00: af00 add r7, sp, #0 8003d02: 60f8 str r0, [r7, #12] 8003d04: 460b mov r3, r1 8003d06: 607a str r2, [r7, #4] 8003d08: 72fb strb r3, [r7, #11] uint32_t response_r1; uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. The SDIO_CMDTIMEOUT is expressed in ms */ uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); 8003d0a: 4b35 ldr r3, [pc, #212] @ (8003de0 ) 8003d0c: 681b ldr r3, [r3, #0] 8003d0e: 4a35 ldr r2, [pc, #212] @ (8003de4 ) 8003d10: fba2 2303 umull r2, r3, r2, r3 8003d14: 0a5b lsrs r3, r3, #9 8003d16: f241 3288 movw r2, #5000 @ 0x1388 8003d1a: fb02 f303 mul.w r3, r2, r3 8003d1e: 61fb str r3, [r7, #28] do { if (count-- == 0U) 8003d20: 69fb ldr r3, [r7, #28] 8003d22: 1e5a subs r2, r3, #1 8003d24: 61fa str r2, [r7, #28] 8003d26: 2b00 cmp r3, #0 8003d28: d102 bne.n 8003d30 { return SDMMC_ERROR_TIMEOUT; 8003d2a: f04f 4300 mov.w r3, #2147483648 @ 0x80000000 8003d2e: e052 b.n 8003dd6 } sta_reg = SDIOx->STA; 8003d30: 68fb ldr r3, [r7, #12] 8003d32: 6b5b ldr r3, [r3, #52] @ 0x34 8003d34: 61bb str r3, [r7, #24] }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) || 8003d36: 69bb ldr r3, [r7, #24] 8003d38: f003 0345 and.w r3, r3, #69 @ 0x45 8003d3c: 2b00 cmp r3, #0 8003d3e: d0ef beq.n 8003d20 ((sta_reg & SDIO_FLAG_CMDACT) != 0U )); 8003d40: 69bb ldr r3, [r7, #24] 8003d42: f403 6300 and.w r3, r3, #2048 @ 0x800 }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) || 8003d46: 2b00 cmp r3, #0 8003d48: d1ea bne.n 8003d20 if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT)) 8003d4a: 68fb ldr r3, [r7, #12] 8003d4c: 6b5b ldr r3, [r3, #52] @ 0x34 8003d4e: f003 0304 and.w r3, r3, #4 8003d52: 2b00 cmp r3, #0 8003d54: d004 beq.n 8003d60 { __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT); 8003d56: 68fb ldr r3, [r7, #12] 8003d58: 2204 movs r2, #4 8003d5a: 639a str r2, [r3, #56] @ 0x38 return SDMMC_ERROR_CMD_RSP_TIMEOUT; 8003d5c: 2304 movs r3, #4 8003d5e: e03a b.n 8003dd6 } else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL)) 8003d60: 68fb ldr r3, [r7, #12] 8003d62: 6b5b ldr r3, [r3, #52] @ 0x34 8003d64: f003 0301 and.w r3, r3, #1 8003d68: 2b00 cmp r3, #0 8003d6a: d004 beq.n 8003d76 { __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL); 8003d6c: 68fb ldr r3, [r7, #12] 8003d6e: 2201 movs r2, #1 8003d70: 639a str r2, [r3, #56] @ 0x38 return SDMMC_ERROR_CMD_CRC_FAIL; 8003d72: 2301 movs r3, #1 8003d74: e02f b.n 8003dd6 { /* Nothing to do */ } /* Check response received is of desired command */ if(SDIO_GetCommandResponse(SDIOx) != SD_CMD) 8003d76: 68f8 ldr r0, [r7, #12] 8003d78: f7ff fc13 bl 80035a2 8003d7c: 4603 mov r3, r0 8003d7e: 461a mov r2, r3 8003d80: 7afb ldrb r3, [r7, #11] 8003d82: 4293 cmp r3, r2 8003d84: d001 beq.n 8003d8a { return SDMMC_ERROR_CMD_CRC_FAIL; 8003d86: 2301 movs r3, #1 8003d88: e025 b.n 8003dd6 } /* Clear all the static flags */ __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS); 8003d8a: 68fb ldr r3, [r7, #12] 8003d8c: 22c5 movs r2, #197 @ 0xc5 8003d8e: 639a str r2, [r3, #56] @ 0x38 /* We have received response, retrieve it. */ response_r1 = SDIO_GetResponse(SDIOx, SDIO_RESP1); 8003d90: 2100 movs r1, #0 8003d92: 68f8 ldr r0, [r7, #12] 8003d94: f7ff fc11 bl 80035ba 8003d98: 6178 str r0, [r7, #20] if((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO) 8003d9a: 697b ldr r3, [r7, #20] 8003d9c: f403 4360 and.w r3, r3, #57344 @ 0xe000 8003da0: 2b00 cmp r3, #0 8003da2: d106 bne.n 8003db2 { *pRCA = (uint16_t) (response_r1 >> 16); 8003da4: 697b ldr r3, [r7, #20] 8003da6: 0c1b lsrs r3, r3, #16 8003da8: b29a uxth r2, r3 8003daa: 687b ldr r3, [r7, #4] 8003dac: 801a strh r2, [r3, #0] return SDMMC_ERROR_NONE; 8003dae: 2300 movs r3, #0 8003db0: e011 b.n 8003dd6 } else if((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD) 8003db2: 697b ldr r3, [r7, #20] 8003db4: f403 4380 and.w r3, r3, #16384 @ 0x4000 8003db8: 2b00 cmp r3, #0 8003dba: d002 beq.n 8003dc2 { return SDMMC_ERROR_ILLEGAL_CMD; 8003dbc: f44f 5300 mov.w r3, #8192 @ 0x2000 8003dc0: e009 b.n 8003dd6 } else if((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED) 8003dc2: 697b ldr r3, [r7, #20] 8003dc4: f403 4300 and.w r3, r3, #32768 @ 0x8000 8003dc8: 2b00 cmp r3, #0 8003dca: d002 beq.n 8003dd2 { return SDMMC_ERROR_COM_CRC_FAILED; 8003dcc: f44f 5380 mov.w r3, #4096 @ 0x1000 8003dd0: e001 b.n 8003dd6 } else { return SDMMC_ERROR_GENERAL_UNKNOWN_ERR; 8003dd2: f44f 3380 mov.w r3, #65536 @ 0x10000 } } 8003dd6: 4618 mov r0, r3 8003dd8: 3720 adds r7, #32 8003dda: 46bd mov sp, r7 8003ddc: bd80 pop {r7, pc} 8003dde: bf00 nop 8003de0: 20000000 .word 0x20000000 8003de4: 10624dd3 .word 0x10624dd3 08003de8 : * @brief Checks for error conditions for R7 response. * @param SDIOx Pointer to SDMMC register base * @retval SD Card error state */ uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx) { 8003de8: b480 push {r7} 8003dea: b085 sub sp, #20 8003dec: af00 add r7, sp, #0 8003dee: 6078 str r0, [r7, #4] uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. The SDIO_CMDTIMEOUT is expressed in ms */ uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); 8003df0: 4b22 ldr r3, [pc, #136] @ (8003e7c ) 8003df2: 681b ldr r3, [r3, #0] 8003df4: 4a22 ldr r2, [pc, #136] @ (8003e80 ) 8003df6: fba2 2303 umull r2, r3, r2, r3 8003dfa: 0a5b lsrs r3, r3, #9 8003dfc: f241 3288 movw r2, #5000 @ 0x1388 8003e00: fb02 f303 mul.w r3, r2, r3 8003e04: 60fb str r3, [r7, #12] do { if (count-- == 0U) 8003e06: 68fb ldr r3, [r7, #12] 8003e08: 1e5a subs r2, r3, #1 8003e0a: 60fa str r2, [r7, #12] 8003e0c: 2b00 cmp r3, #0 8003e0e: d102 bne.n 8003e16 { return SDMMC_ERROR_TIMEOUT; 8003e10: f04f 4300 mov.w r3, #2147483648 @ 0x80000000 8003e14: e02c b.n 8003e70 } sta_reg = SDIOx->STA; 8003e16: 687b ldr r3, [r7, #4] 8003e18: 6b5b ldr r3, [r3, #52] @ 0x34 8003e1a: 60bb str r3, [r7, #8] }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) || 8003e1c: 68bb ldr r3, [r7, #8] 8003e1e: f003 0345 and.w r3, r3, #69 @ 0x45 8003e22: 2b00 cmp r3, #0 8003e24: d0ef beq.n 8003e06 ((sta_reg & SDIO_FLAG_CMDACT) != 0U )); 8003e26: 68bb ldr r3, [r7, #8] 8003e28: f403 6300 and.w r3, r3, #2048 @ 0x800 }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) || 8003e2c: 2b00 cmp r3, #0 8003e2e: d1ea bne.n 8003e06 if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT)) 8003e30: 687b ldr r3, [r7, #4] 8003e32: 6b5b ldr r3, [r3, #52] @ 0x34 8003e34: f003 0304 and.w r3, r3, #4 8003e38: 2b00 cmp r3, #0 8003e3a: d004 beq.n 8003e46 { /* Card is SD V2.0 compliant */ __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT); 8003e3c: 687b ldr r3, [r7, #4] 8003e3e: 2204 movs r2, #4 8003e40: 639a str r2, [r3, #56] @ 0x38 return SDMMC_ERROR_CMD_RSP_TIMEOUT; 8003e42: 2304 movs r3, #4 8003e44: e014 b.n 8003e70 } else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL)) 8003e46: 687b ldr r3, [r7, #4] 8003e48: 6b5b ldr r3, [r3, #52] @ 0x34 8003e4a: f003 0301 and.w r3, r3, #1 8003e4e: 2b00 cmp r3, #0 8003e50: d004 beq.n 8003e5c { /* Card is SD V2.0 compliant */ __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL); 8003e52: 687b ldr r3, [r7, #4] 8003e54: 2201 movs r2, #1 8003e56: 639a str r2, [r3, #56] @ 0x38 return SDMMC_ERROR_CMD_CRC_FAIL; 8003e58: 2301 movs r3, #1 8003e5a: e009 b.n 8003e70 else { /* Nothing to do */ } if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDREND)) 8003e5c: 687b ldr r3, [r7, #4] 8003e5e: 6b5b ldr r3, [r3, #52] @ 0x34 8003e60: f003 0340 and.w r3, r3, #64 @ 0x40 8003e64: 2b00 cmp r3, #0 8003e66: d002 beq.n 8003e6e { /* Card is SD V2.0 compliant */ __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CMDREND); 8003e68: 687b ldr r3, [r7, #4] 8003e6a: 2240 movs r2, #64 @ 0x40 8003e6c: 639a str r2, [r3, #56] @ 0x38 } return SDMMC_ERROR_NONE; 8003e6e: 2300 movs r3, #0 } 8003e70: 4618 mov r0, r3 8003e72: 3714 adds r7, #20 8003e74: 46bd mov sp, r7 8003e76: bc80 pop {r7} 8003e78: 4770 bx lr 8003e7a: bf00 nop 8003e7c: 20000000 .word 0x20000000 8003e80: 10624dd3 .word 0x10624dd3 08003e84 : * @brief Checks for error conditions for CMD0. * @param SDIOx Pointer to SDMMC register base * @retval SD Card error state */ static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx) { 8003e84: b480 push {r7} 8003e86: b085 sub sp, #20 8003e88: af00 add r7, sp, #0 8003e8a: 6078 str r0, [r7, #4] /* 8 is the number of required instructions cycles for the below loop statement. The SDIO_CMDTIMEOUT is expressed in ms */ uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); 8003e8c: 4b10 ldr r3, [pc, #64] @ (8003ed0 ) 8003e8e: 681b ldr r3, [r3, #0] 8003e90: 4a10 ldr r2, [pc, #64] @ (8003ed4 ) 8003e92: fba2 2303 umull r2, r3, r2, r3 8003e96: 0a5b lsrs r3, r3, #9 8003e98: f241 3288 movw r2, #5000 @ 0x1388 8003e9c: fb02 f303 mul.w r3, r2, r3 8003ea0: 60fb str r3, [r7, #12] do { if (count-- == 0U) 8003ea2: 68fb ldr r3, [r7, #12] 8003ea4: 1e5a subs r2, r3, #1 8003ea6: 60fa str r2, [r7, #12] 8003ea8: 2b00 cmp r3, #0 8003eaa: d102 bne.n 8003eb2 { return SDMMC_ERROR_TIMEOUT; 8003eac: f04f 4300 mov.w r3, #2147483648 @ 0x80000000 8003eb0: e009 b.n 8003ec6 } }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDSENT)); 8003eb2: 687b ldr r3, [r7, #4] 8003eb4: 6b5b ldr r3, [r3, #52] @ 0x34 8003eb6: f003 0380 and.w r3, r3, #128 @ 0x80 8003eba: 2b00 cmp r3, #0 8003ebc: d0f1 beq.n 8003ea2 /* Clear all the static flags */ __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS); 8003ebe: 687b ldr r3, [r7, #4] 8003ec0: 22c5 movs r2, #197 @ 0xc5 8003ec2: 639a str r2, [r3, #56] @ 0x38 return SDMMC_ERROR_NONE; 8003ec4: 2300 movs r3, #0 } 8003ec6: 4618 mov r0, r3 8003ec8: 3714 adds r7, #20 8003eca: 46bd mov sp, r7 8003ecc: bc80 pop {r7} 8003ece: 4770 bx lr 8003ed0: 20000000 .word 0x20000000 8003ed4: 10624dd3 .word 0x10624dd3 08003ed8 : /* USER CODE BEGIN Variables */ /* USER CODE END Variables */ void MX_FATFS_Init(void) { 8003ed8: b580 push {r7, lr} 8003eda: af00 add r7, sp, #0 /*## FatFS: Link the SD driver ###########################*/ retSD = FATFS_LinkDriver(&SD_Driver, SDPath); 8003edc: 4904 ldr r1, [pc, #16] @ (8003ef0 ) 8003ede: 4805 ldr r0, [pc, #20] @ (8003ef4 ) 8003ee0: f000 f8f0 bl 80040c4 8003ee4: 4603 mov r3, r0 8003ee6: 461a mov r2, r3 8003ee8: 4b03 ldr r3, [pc, #12] @ (8003ef8 ) 8003eea: 701a strb r2, [r3, #0] /* USER CODE BEGIN Init */ /* additional user code for init */ /* USER CODE END Init */ } 8003eec: bf00 nop 8003eee: bd80 pop {r7, pc} 8003ef0: 20000194 .word 0x20000194 8003ef4: 0800435c .word 0x0800435c 8003ef8: 20000190 .word 0x20000190 08003efc : /** * @brief Initializes the SD card device. * @retval SD status */ __weak uint8_t BSP_SD_Init(void) { 8003efc: b580 push {r7, lr} 8003efe: b082 sub sp, #8 8003f00: af00 add r7, sp, #0 uint8_t sd_state = MSD_OK; 8003f02: 2300 movs r3, #0 8003f04: 71fb strb r3, [r7, #7] /* Check if the SD card is plugged in the slot */ if (BSP_SD_IsDetected() != SD_PRESENT) 8003f06: f000 f86b bl 8003fe0 8003f0a: 4603 mov r3, r0 8003f0c: 2b01 cmp r3, #1 8003f0e: d001 beq.n 8003f14 { return MSD_ERROR; 8003f10: 2301 movs r3, #1 8003f12: e005 b.n 8003f20 } /* HAL SD initialization */ sd_state = HAL_SD_Init(&hsd); 8003f14: 4804 ldr r0, [pc, #16] @ (8003f28 ) 8003f16: f7fd fdf9 bl 8001b0c 8003f1a: 4603 mov r3, r0 8003f1c: 71fb strb r3, [r7, #7] return sd_state; 8003f1e: 79fb ldrb r3, [r7, #7] } 8003f20: 4618 mov r0, r3 8003f22: 3708 adds r7, #8 8003f24: 46bd mov sp, r7 8003f26: bd80 pop {r7, pc} 8003f28: 20000030 .word 0x20000030 08003f2c : * @param NumOfBlocks: Number of SD blocks to read * @param Timeout: Timeout for read operation * @retval SD status */ __weak uint8_t BSP_SD_ReadBlocks(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks, uint32_t Timeout) { 8003f2c: b580 push {r7, lr} 8003f2e: b088 sub sp, #32 8003f30: af02 add r7, sp, #8 8003f32: 60f8 str r0, [r7, #12] 8003f34: 60b9 str r1, [r7, #8] 8003f36: 607a str r2, [r7, #4] 8003f38: 603b str r3, [r7, #0] uint8_t sd_state = MSD_OK; 8003f3a: 2300 movs r3, #0 8003f3c: 75fb strb r3, [r7, #23] if (HAL_SD_ReadBlocks(&hsd, (uint8_t *)pData, ReadAddr, NumOfBlocks, Timeout) != HAL_OK) 8003f3e: 683b ldr r3, [r7, #0] 8003f40: 9300 str r3, [sp, #0] 8003f42: 687b ldr r3, [r7, #4] 8003f44: 68ba ldr r2, [r7, #8] 8003f46: 68f9 ldr r1, [r7, #12] 8003f48: 4806 ldr r0, [pc, #24] @ (8003f64 ) 8003f4a: f7fd fe87 bl 8001c5c 8003f4e: 4603 mov r3, r0 8003f50: 2b00 cmp r3, #0 8003f52: d001 beq.n 8003f58 { sd_state = MSD_ERROR; 8003f54: 2301 movs r3, #1 8003f56: 75fb strb r3, [r7, #23] } return sd_state; 8003f58: 7dfb ldrb r3, [r7, #23] } 8003f5a: 4618 mov r0, r3 8003f5c: 3718 adds r7, #24 8003f5e: 46bd mov sp, r7 8003f60: bd80 pop {r7, pc} 8003f62: bf00 nop 8003f64: 20000030 .word 0x20000030 08003f68 : * @param NumOfBlocks: Number of SD blocks to write * @param Timeout: Timeout for write operation * @retval SD status */ __weak uint8_t BSP_SD_WriteBlocks(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks, uint32_t Timeout) { 8003f68: b580 push {r7, lr} 8003f6a: b088 sub sp, #32 8003f6c: af02 add r7, sp, #8 8003f6e: 60f8 str r0, [r7, #12] 8003f70: 60b9 str r1, [r7, #8] 8003f72: 607a str r2, [r7, #4] 8003f74: 603b str r3, [r7, #0] uint8_t sd_state = MSD_OK; 8003f76: 2300 movs r3, #0 8003f78: 75fb strb r3, [r7, #23] if (HAL_SD_WriteBlocks(&hsd, (uint8_t *)pData, WriteAddr, NumOfBlocks, Timeout) != HAL_OK) 8003f7a: 683b ldr r3, [r7, #0] 8003f7c: 9300 str r3, [sp, #0] 8003f7e: 687b ldr r3, [r7, #4] 8003f80: 68ba ldr r2, [r7, #8] 8003f82: 68f9 ldr r1, [r7, #12] 8003f84: 4806 ldr r0, [pc, #24] @ (8003fa0 ) 8003f86: f7fe f84f bl 8002028 8003f8a: 4603 mov r3, r0 8003f8c: 2b00 cmp r3, #0 8003f8e: d001 beq.n 8003f94 { sd_state = MSD_ERROR; 8003f90: 2301 movs r3, #1 8003f92: 75fb strb r3, [r7, #23] } return sd_state; 8003f94: 7dfb ldrb r3, [r7, #23] } 8003f96: 4618 mov r0, r3 8003f98: 3718 adds r7, #24 8003f9a: 46bd mov sp, r7 8003f9c: bd80 pop {r7, pc} 8003f9e: bf00 nop 8003fa0: 20000030 .word 0x20000030 08003fa4 : * This value can be one of the following values: * @arg SD_TRANSFER_OK: No data transfer is acting * @arg SD_TRANSFER_BUSY: Data transfer is acting */ __weak uint8_t BSP_SD_GetCardState(void) { 8003fa4: b580 push {r7, lr} 8003fa6: af00 add r7, sp, #0 return ((HAL_SD_GetCardState(&hsd) == HAL_SD_CARD_TRANSFER ) ? SD_TRANSFER_OK : SD_TRANSFER_BUSY); 8003fa8: 4805 ldr r0, [pc, #20] @ (8003fc0 ) 8003faa: f7fe fb9a bl 80026e2 8003fae: 4603 mov r3, r0 8003fb0: 2b04 cmp r3, #4 8003fb2: bf14 ite ne 8003fb4: 2301 movne r3, #1 8003fb6: 2300 moveq r3, #0 8003fb8: b2db uxtb r3, r3 } 8003fba: 4618 mov r0, r3 8003fbc: bd80 pop {r7, pc} 8003fbe: bf00 nop 8003fc0: 20000030 .word 0x20000030 08003fc4 : * @brief Get SD information about specific SD card. * @param CardInfo: Pointer to HAL_SD_CardInfoTypedef structure * @retval None */ __weak void BSP_SD_GetCardInfo(HAL_SD_CardInfoTypeDef *CardInfo) { 8003fc4: b580 push {r7, lr} 8003fc6: b082 sub sp, #8 8003fc8: af00 add r7, sp, #0 8003fca: 6078 str r0, [r7, #4] /* Get SD card Information */ HAL_SD_GetCardInfo(&hsd, CardInfo); 8003fcc: 6879 ldr r1, [r7, #4] 8003fce: 4803 ldr r0, [pc, #12] @ (8003fdc ) 8003fd0: f7fe fb5c bl 800268c } 8003fd4: bf00 nop 8003fd6: 3708 adds r7, #8 8003fd8: 46bd mov sp, r7 8003fda: bd80 pop {r7, pc} 8003fdc: 20000030 .word 0x20000030 08003fe0 : * @brief Detects if SD card is correctly plugged in the memory slot or not. * @param None * @retval Returns if SD is detected or not */ __weak uint8_t BSP_SD_IsDetected(void) { 8003fe0: b580 push {r7, lr} 8003fe2: b082 sub sp, #8 8003fe4: af00 add r7, sp, #0 __IO uint8_t status = SD_PRESENT; 8003fe6: 2301 movs r3, #1 8003fe8: 71fb strb r3, [r7, #7] if (BSP_PlatformIsDetected() == 0x0) 8003fea: f000 f80b bl 8004004 8003fee: 4603 mov r3, r0 8003ff0: 2b00 cmp r3, #0 8003ff2: d101 bne.n 8003ff8 { status = SD_NOT_PRESENT; 8003ff4: 2300 movs r3, #0 8003ff6: 71fb strb r3, [r7, #7] } return status; 8003ff8: 79fb ldrb r3, [r7, #7] 8003ffa: b2db uxtb r3, r3 } 8003ffc: 4618 mov r0, r3 8003ffe: 3708 adds r7, #8 8004000: 46bd mov sp, r7 8004002: bd80 pop {r7, pc} 08004004 : ****************************************************************************** */ /* USER CODE END Header */ #include "fatfs_platform.h" uint8_t BSP_PlatformIsDetected(void) { 8004004: b580 push {r7, lr} 8004006: b082 sub sp, #8 8004008: af00 add r7, sp, #0 uint8_t status = SD_PRESENT; 800400a: 2301 movs r3, #1 800400c: 71fb strb r3, [r7, #7] /* Check SD card detect pin */ if(HAL_GPIO_ReadPin(SD_DETECT_GPIO_PORT, SD_DETECT_PIN) != GPIO_PIN_RESET) 800400e: 2108 movs r1, #8 8004010: 4806 ldr r0, [pc, #24] @ (800402c ) 8004012: f7fd f921 bl 8001258 8004016: 4603 mov r3, r0 8004018: 2b00 cmp r3, #0 800401a: d001 beq.n 8004020 { status = SD_NOT_PRESENT; 800401c: 2300 movs r3, #0 800401e: 71fb strb r3, [r7, #7] } /* USER CODE BEGIN 1 */ /* user code can be inserted here */ /* USER CODE END 1 */ return status; 8004020: 79fb ldrb r3, [r7, #7] } 8004022: 4618 mov r0, r3 8004024: 3708 adds r7, #8 8004026: 46bd mov sp, r7 8004028: bd80 pop {r7, pc} 800402a: bf00 nop 800402c: 40011800 .word 0x40011800 08004030 : * @param lun : only used for USB Key Disk to add multi-lun management else the paramter must be equal to 0 * @retval Returns 0 in case of success, otherwise 1. */ uint8_t FATFS_LinkDriverEx(Diskio_drvTypeDef *drv, char *path, uint8_t lun) { 8004030: b480 push {r7} 8004032: b087 sub sp, #28 8004034: af00 add r7, sp, #0 8004036: 60f8 str r0, [r7, #12] 8004038: 60b9 str r1, [r7, #8] 800403a: 4613 mov r3, r2 800403c: 71fb strb r3, [r7, #7] uint8_t ret = 1; 800403e: 2301 movs r3, #1 8004040: 75fb strb r3, [r7, #23] uint8_t DiskNum = 0; 8004042: 2300 movs r3, #0 8004044: 75bb strb r3, [r7, #22] if(disk.nbr <= _VOLUMES) 8004046: 4b1e ldr r3, [pc, #120] @ (80040c0 ) 8004048: 7a5b ldrb r3, [r3, #9] 800404a: b2db uxtb r3, r3 800404c: 2b01 cmp r3, #1 800404e: d831 bhi.n 80040b4 { disk.is_initialized[disk.nbr] = 0; 8004050: 4b1b ldr r3, [pc, #108] @ (80040c0 ) 8004052: 7a5b ldrb r3, [r3, #9] 8004054: b2db uxtb r3, r3 8004056: 461a mov r2, r3 8004058: 4b19 ldr r3, [pc, #100] @ (80040c0 ) 800405a: 2100 movs r1, #0 800405c: 5499 strb r1, [r3, r2] disk.drv[disk.nbr] = drv; 800405e: 4b18 ldr r3, [pc, #96] @ (80040c0 ) 8004060: 7a5b ldrb r3, [r3, #9] 8004062: b2db uxtb r3, r3 8004064: 4a16 ldr r2, [pc, #88] @ (80040c0 ) 8004066: 009b lsls r3, r3, #2 8004068: 4413 add r3, r2 800406a: 68fa ldr r2, [r7, #12] 800406c: 605a str r2, [r3, #4] disk.lun[disk.nbr] = lun; 800406e: 4b14 ldr r3, [pc, #80] @ (80040c0 ) 8004070: 7a5b ldrb r3, [r3, #9] 8004072: b2db uxtb r3, r3 8004074: 461a mov r2, r3 8004076: 4b12 ldr r3, [pc, #72] @ (80040c0 ) 8004078: 4413 add r3, r2 800407a: 79fa ldrb r2, [r7, #7] 800407c: 721a strb r2, [r3, #8] DiskNum = disk.nbr++; 800407e: 4b10 ldr r3, [pc, #64] @ (80040c0 ) 8004080: 7a5b ldrb r3, [r3, #9] 8004082: b2db uxtb r3, r3 8004084: 1c5a adds r2, r3, #1 8004086: b2d1 uxtb r1, r2 8004088: 4a0d ldr r2, [pc, #52] @ (80040c0 ) 800408a: 7251 strb r1, [r2, #9] 800408c: 75bb strb r3, [r7, #22] path[0] = DiskNum + '0'; 800408e: 7dbb ldrb r3, [r7, #22] 8004090: 3330 adds r3, #48 @ 0x30 8004092: b2da uxtb r2, r3 8004094: 68bb ldr r3, [r7, #8] 8004096: 701a strb r2, [r3, #0] path[1] = ':'; 8004098: 68bb ldr r3, [r7, #8] 800409a: 3301 adds r3, #1 800409c: 223a movs r2, #58 @ 0x3a 800409e: 701a strb r2, [r3, #0] path[2] = '/'; 80040a0: 68bb ldr r3, [r7, #8] 80040a2: 3302 adds r3, #2 80040a4: 222f movs r2, #47 @ 0x2f 80040a6: 701a strb r2, [r3, #0] path[3] = 0; 80040a8: 68bb ldr r3, [r7, #8] 80040aa: 3303 adds r3, #3 80040ac: 2200 movs r2, #0 80040ae: 701a strb r2, [r3, #0] ret = 0; 80040b0: 2300 movs r3, #0 80040b2: 75fb strb r3, [r7, #23] } return ret; 80040b4: 7dfb ldrb r3, [r7, #23] } 80040b6: 4618 mov r0, r3 80040b8: 371c adds r7, #28 80040ba: 46bd mov sp, r7 80040bc: bc80 pop {r7} 80040be: 4770 bx lr 80040c0: 20000198 .word 0x20000198 080040c4 : * @param drv: pointer to the disk IO Driver structure * @param path: pointer to the logical drive path * @retval Returns 0 in case of success, otherwise 1. */ uint8_t FATFS_LinkDriver(Diskio_drvTypeDef *drv, char *path) { 80040c4: b580 push {r7, lr} 80040c6: b082 sub sp, #8 80040c8: af00 add r7, sp, #0 80040ca: 6078 str r0, [r7, #4] 80040cc: 6039 str r1, [r7, #0] return FATFS_LinkDriverEx(drv, path, 0); 80040ce: 2200 movs r2, #0 80040d0: 6839 ldr r1, [r7, #0] 80040d2: 6878 ldr r0, [r7, #4] 80040d4: f7ff ffac bl 8004030 80040d8: 4603 mov r3, r0 } 80040da: 4618 mov r0, r3 80040dc: 3708 adds r7, #8 80040de: 46bd mov sp, r7 80040e0: bd80 pop {r7, pc} ... 080040e4 : * @brief Initializes a Drive * @param lun : not used * @retval DSTATUS: Operation status */ DSTATUS SD_initialize(BYTE lun) { 80040e4: b580 push {r7, lr} 80040e6: b082 sub sp, #8 80040e8: af00 add r7, sp, #0 80040ea: 4603 mov r3, r0 80040ec: 71fb strb r3, [r7, #7] Stat = STA_NOINIT; 80040ee: 4b0b ldr r3, [pc, #44] @ (800411c ) 80040f0: 2201 movs r2, #1 80040f2: 701a strb r2, [r3, #0] /* Configure the uSD device */ if(BSP_SD_Init() == MSD_OK) 80040f4: f7ff ff02 bl 8003efc 80040f8: 4603 mov r3, r0 80040fa: 2b00 cmp r3, #0 80040fc: d107 bne.n 800410e { Stat &= ~STA_NOINIT; 80040fe: 4b07 ldr r3, [pc, #28] @ (800411c ) 8004100: 781b ldrb r3, [r3, #0] 8004102: b2db uxtb r3, r3 8004104: f023 0301 bic.w r3, r3, #1 8004108: b2da uxtb r2, r3 800410a: 4b04 ldr r3, [pc, #16] @ (800411c ) 800410c: 701a strb r2, [r3, #0] } return Stat; 800410e: 4b03 ldr r3, [pc, #12] @ (800411c ) 8004110: 781b ldrb r3, [r3, #0] 8004112: b2db uxtb r3, r3 } 8004114: 4618 mov r0, r3 8004116: 3708 adds r7, #8 8004118: 46bd mov sp, r7 800411a: bd80 pop {r7, pc} 800411c: 20000009 .word 0x20000009 08004120 : * @brief Gets Disk Status * @param lun : not used * @retval DSTATUS: Operation status */ DSTATUS SD_status(BYTE lun) { 8004120: b580 push {r7, lr} 8004122: b082 sub sp, #8 8004124: af00 add r7, sp, #0 8004126: 4603 mov r3, r0 8004128: 71fb strb r3, [r7, #7] Stat = STA_NOINIT; 800412a: 4b0b ldr r3, [pc, #44] @ (8004158 ) 800412c: 2201 movs r2, #1 800412e: 701a strb r2, [r3, #0] if(BSP_SD_GetCardState() == MSD_OK) 8004130: f7ff ff38 bl 8003fa4 8004134: 4603 mov r3, r0 8004136: 2b00 cmp r3, #0 8004138: d107 bne.n 800414a { Stat &= ~STA_NOINIT; 800413a: 4b07 ldr r3, [pc, #28] @ (8004158 ) 800413c: 781b ldrb r3, [r3, #0] 800413e: b2db uxtb r3, r3 8004140: f023 0301 bic.w r3, r3, #1 8004144: b2da uxtb r2, r3 8004146: 4b04 ldr r3, [pc, #16] @ (8004158 ) 8004148: 701a strb r2, [r3, #0] } return Stat; 800414a: 4b03 ldr r3, [pc, #12] @ (8004158 ) 800414c: 781b ldrb r3, [r3, #0] 800414e: b2db uxtb r3, r3 } 8004150: 4618 mov r0, r3 8004152: 3708 adds r7, #8 8004154: 46bd mov sp, r7 8004156: bd80 pop {r7, pc} 8004158: 20000009 .word 0x20000009 0800415c : * @param sector: Sector address (LBA) * @param count: Number of sectors to read (1..128) * @retval DRESULT: Operation result */ DRESULT SD_read(BYTE lun, BYTE *buff, DWORD sector, UINT count) { 800415c: b580 push {r7, lr} 800415e: b086 sub sp, #24 8004160: af00 add r7, sp, #0 8004162: 60b9 str r1, [r7, #8] 8004164: 607a str r2, [r7, #4] 8004166: 603b str r3, [r7, #0] 8004168: 4603 mov r3, r0 800416a: 73fb strb r3, [r7, #15] DRESULT res = RES_ERROR; 800416c: 2301 movs r3, #1 800416e: 75fb strb r3, [r7, #23] uint32_t timeout = 100000; 8004170: 4b0f ldr r3, [pc, #60] @ (80041b0 ) 8004172: 613b str r3, [r7, #16] if(BSP_SD_ReadBlocks((uint32_t*)buff, 8004174: 4b0f ldr r3, [pc, #60] @ (80041b4 ) 8004176: 683a ldr r2, [r7, #0] 8004178: 6879 ldr r1, [r7, #4] 800417a: 68b8 ldr r0, [r7, #8] 800417c: f7ff fed6 bl 8003f2c 8004180: 4603 mov r3, r0 8004182: 2b00 cmp r3, #0 8004184: d10e bne.n 80041a4 (uint32_t) (sector), count, SD_DATATIMEOUT) == MSD_OK) { while(BSP_SD_GetCardState()!= MSD_OK) 8004186: e006 b.n 8004196 { if (timeout-- == 0) 8004188: 693b ldr r3, [r7, #16] 800418a: 1e5a subs r2, r3, #1 800418c: 613a str r2, [r7, #16] 800418e: 2b00 cmp r3, #0 8004190: d101 bne.n 8004196 { return RES_ERROR; 8004192: 2301 movs r3, #1 8004194: e007 b.n 80041a6 while(BSP_SD_GetCardState()!= MSD_OK) 8004196: f7ff ff05 bl 8003fa4 800419a: 4603 mov r3, r0 800419c: 2b00 cmp r3, #0 800419e: d1f3 bne.n 8004188 } } res = RES_OK; 80041a0: 2300 movs r3, #0 80041a2: 75fb strb r3, [r7, #23] } return res; 80041a4: 7dfb ldrb r3, [r7, #23] } 80041a6: 4618 mov r0, r3 80041a8: 3718 adds r7, #24 80041aa: 46bd mov sp, r7 80041ac: bd80 pop {r7, pc} 80041ae: bf00 nop 80041b0: 000186a0 .word 0x000186a0 80041b4: 05f5e100 .word 0x05f5e100 080041b8 : * @param count: Number of sectors to write (1..128) * @retval DRESULT: Operation result */ #if _USE_WRITE == 1 DRESULT SD_write(BYTE lun, const BYTE *buff, DWORD sector, UINT count) { 80041b8: b580 push {r7, lr} 80041ba: b086 sub sp, #24 80041bc: af00 add r7, sp, #0 80041be: 60b9 str r1, [r7, #8] 80041c0: 607a str r2, [r7, #4] 80041c2: 603b str r3, [r7, #0] 80041c4: 4603 mov r3, r0 80041c6: 73fb strb r3, [r7, #15] DRESULT res = RES_ERROR; 80041c8: 2301 movs r3, #1 80041ca: 75fb strb r3, [r7, #23] uint32_t timeout = 100000; 80041cc: 4b0f ldr r3, [pc, #60] @ (800420c ) 80041ce: 613b str r3, [r7, #16] if(BSP_SD_WriteBlocks((uint32_t*)buff, 80041d0: 4b0f ldr r3, [pc, #60] @ (8004210 ) 80041d2: 683a ldr r2, [r7, #0] 80041d4: 6879 ldr r1, [r7, #4] 80041d6: 68b8 ldr r0, [r7, #8] 80041d8: f7ff fec6 bl 8003f68 80041dc: 4603 mov r3, r0 80041de: 2b00 cmp r3, #0 80041e0: d10e bne.n 8004200 (uint32_t)(sector), count, SD_DATATIMEOUT) == MSD_OK) { while(BSP_SD_GetCardState()!= MSD_OK) 80041e2: e006 b.n 80041f2 { if (timeout-- == 0) 80041e4: 693b ldr r3, [r7, #16] 80041e6: 1e5a subs r2, r3, #1 80041e8: 613a str r2, [r7, #16] 80041ea: 2b00 cmp r3, #0 80041ec: d101 bne.n 80041f2 { return RES_ERROR; 80041ee: 2301 movs r3, #1 80041f0: e007 b.n 8004202 while(BSP_SD_GetCardState()!= MSD_OK) 80041f2: f7ff fed7 bl 8003fa4 80041f6: 4603 mov r3, r0 80041f8: 2b00 cmp r3, #0 80041fa: d1f3 bne.n 80041e4 } } res = RES_OK; 80041fc: 2300 movs r3, #0 80041fe: 75fb strb r3, [r7, #23] } return res; 8004200: 7dfb ldrb r3, [r7, #23] } 8004202: 4618 mov r0, r3 8004204: 3718 adds r7, #24 8004206: 46bd mov sp, r7 8004208: bd80 pop {r7, pc} 800420a: bf00 nop 800420c: 000186a0 .word 0x000186a0 8004210: 05f5e100 .word 0x05f5e100 08004214 : * @param *buff: Buffer to send/receive control data * @retval DRESULT: Operation result */ #if _USE_IOCTL == 1 DRESULT SD_ioctl(BYTE lun, BYTE cmd, void *buff) { 8004214: b580 push {r7, lr} 8004216: b08c sub sp, #48 @ 0x30 8004218: af00 add r7, sp, #0 800421a: 4603 mov r3, r0 800421c: 603a str r2, [r7, #0] 800421e: 71fb strb r3, [r7, #7] 8004220: 460b mov r3, r1 8004222: 71bb strb r3, [r7, #6] DRESULT res = RES_ERROR; 8004224: 2301 movs r3, #1 8004226: f887 302f strb.w r3, [r7, #47] @ 0x2f BSP_SD_CardInfo CardInfo; if (Stat & STA_NOINIT) return RES_NOTRDY; 800422a: 4b24 ldr r3, [pc, #144] @ (80042bc ) 800422c: 781b ldrb r3, [r3, #0] 800422e: b2db uxtb r3, r3 8004230: f003 0301 and.w r3, r3, #1 8004234: 2b00 cmp r3, #0 8004236: d001 beq.n 800423c 8004238: 2303 movs r3, #3 800423a: e03b b.n 80042b4 switch (cmd) 800423c: 79bb ldrb r3, [r7, #6] 800423e: 2b03 cmp r3, #3 8004240: d833 bhi.n 80042aa 8004242: a201 add r2, pc, #4 @ (adr r2, 8004248 ) 8004244: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8004248: 08004259 .word 0x08004259 800424c: 08004261 .word 0x08004261 8004250: 08004279 .word 0x08004279 8004254: 08004293 .word 0x08004293 { /* Make sure that no pending write process */ case CTRL_SYNC : res = RES_OK; 8004258: 2300 movs r3, #0 800425a: f887 302f strb.w r3, [r7, #47] @ 0x2f break; 800425e: e027 b.n 80042b0 /* Get number of sectors on the disk (DWORD) */ case GET_SECTOR_COUNT : BSP_SD_GetCardInfo(&CardInfo); 8004260: f107 030c add.w r3, r7, #12 8004264: 4618 mov r0, r3 8004266: f7ff fead bl 8003fc4 *(DWORD*)buff = CardInfo.LogBlockNbr; 800426a: 6a7a ldr r2, [r7, #36] @ 0x24 800426c: 683b ldr r3, [r7, #0] 800426e: 601a str r2, [r3, #0] res = RES_OK; 8004270: 2300 movs r3, #0 8004272: f887 302f strb.w r3, [r7, #47] @ 0x2f break; 8004276: e01b b.n 80042b0 /* Get R/W sector size (WORD) */ case GET_SECTOR_SIZE : BSP_SD_GetCardInfo(&CardInfo); 8004278: f107 030c add.w r3, r7, #12 800427c: 4618 mov r0, r3 800427e: f7ff fea1 bl 8003fc4 *(WORD*)buff = CardInfo.LogBlockSize; 8004282: 6abb ldr r3, [r7, #40] @ 0x28 8004284: b29a uxth r2, r3 8004286: 683b ldr r3, [r7, #0] 8004288: 801a strh r2, [r3, #0] res = RES_OK; 800428a: 2300 movs r3, #0 800428c: f887 302f strb.w r3, [r7, #47] @ 0x2f break; 8004290: e00e b.n 80042b0 /* Get erase block size in unit of sector (DWORD) */ case GET_BLOCK_SIZE : BSP_SD_GetCardInfo(&CardInfo); 8004292: f107 030c add.w r3, r7, #12 8004296: 4618 mov r0, r3 8004298: f7ff fe94 bl 8003fc4 *(DWORD*)buff = CardInfo.LogBlockSize; 800429c: 6aba ldr r2, [r7, #40] @ 0x28 800429e: 683b ldr r3, [r7, #0] 80042a0: 601a str r2, [r3, #0] res = RES_OK; 80042a2: 2300 movs r3, #0 80042a4: f887 302f strb.w r3, [r7, #47] @ 0x2f break; 80042a8: e002 b.n 80042b0 default: res = RES_PARERR; 80042aa: 2304 movs r3, #4 80042ac: f887 302f strb.w r3, [r7, #47] @ 0x2f } return res; 80042b0: f897 302f ldrb.w r3, [r7, #47] @ 0x2f } 80042b4: 4618 mov r0, r3 80042b6: 3730 adds r7, #48 @ 0x30 80042b8: 46bd mov sp, r7 80042ba: bd80 pop {r7, pc} 80042bc: 20000009 .word 0x20000009 080042c0 : 80042c0: 4603 mov r3, r0 80042c2: 4402 add r2, r0 80042c4: 4293 cmp r3, r2 80042c6: d100 bne.n 80042ca 80042c8: 4770 bx lr 80042ca: f803 1b01 strb.w r1, [r3], #1 80042ce: e7f9 b.n 80042c4 080042d0 <__libc_init_array>: 80042d0: b570 push {r4, r5, r6, lr} 80042d2: 2600 movs r6, #0 80042d4: 4d0c ldr r5, [pc, #48] @ (8004308 <__libc_init_array+0x38>) 80042d6: 4c0d ldr r4, [pc, #52] @ (800430c <__libc_init_array+0x3c>) 80042d8: 1b64 subs r4, r4, r5 80042da: 10a4 asrs r4, r4, #2 80042dc: 42a6 cmp r6, r4 80042de: d109 bne.n 80042f4 <__libc_init_array+0x24> 80042e0: f000 f81a bl 8004318 <_init> 80042e4: 2600 movs r6, #0 80042e6: 4d0a ldr r5, [pc, #40] @ (8004310 <__libc_init_array+0x40>) 80042e8: 4c0a ldr r4, [pc, #40] @ (8004314 <__libc_init_array+0x44>) 80042ea: 1b64 subs r4, r4, r5 80042ec: 10a4 asrs r4, r4, #2 80042ee: 42a6 cmp r6, r4 80042f0: d105 bne.n 80042fe <__libc_init_array+0x2e> 80042f2: bd70 pop {r4, r5, r6, pc} 80042f4: f855 3b04 ldr.w r3, [r5], #4 80042f8: 4798 blx r3 80042fa: 3601 adds r6, #1 80042fc: e7ee b.n 80042dc <__libc_init_array+0xc> 80042fe: f855 3b04 ldr.w r3, [r5], #4 8004302: 4798 blx r3 8004304: 3601 adds r6, #1 8004306: e7f2 b.n 80042ee <__libc_init_array+0x1e> 8004308: 08004370 .word 0x08004370 800430c: 08004370 .word 0x08004370 8004310: 08004370 .word 0x08004370 8004314: 08004374 .word 0x08004374 08004318 <_init>: 8004318: b5f8 push {r3, r4, r5, r6, r7, lr} 800431a: bf00 nop 800431c: bcf8 pop {r3, r4, r5, r6, r7} 800431e: bc08 pop {r3} 8004320: 469e mov lr, r3 8004322: 4770 bx lr 08004324 <_fini>: 8004324: b5f8 push {r3, r4, r5, r6, r7, lr} 8004326: bf00 nop 8004328: bcf8 pop {r3, r4, r5, r6, r7} 800432a: bc08 pop {r3} 800432c: 469e mov lr, r3 800432e: 4770 bx lr